David Scott

Person

Dallas, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for latch-up prevention
- Patent number 11,615,227
- Issue date Mar 28, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Chia Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuits and manufacturing methods thereof
- Patent number 9,385,213
- Issue date Jul 5, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chung-Cheng Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory circuits having a diode-connected transistor with back-biase...
- Patent number 8,804,450
- Issue date Aug 12, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Steven Swei
- G11 - INFORMATION STORAGE
Information Patent Grant
Standard cells having flexible layout architecture/boundaries
- Patent number 8,504,972
- Issue date Aug 6, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for energy harvest from ambient sources
- Patent number 8,432,071
- Issue date Apr 30, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ming-Chieh Huang
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Memory circuits having a diode-connected transistor with back-biase...
- Patent number 8,411,525
- Issue date Apr 2, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Steven Swei
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuits and manufacturing methods thereof
- Patent number 8,362,573
- Issue date Jan 29, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chung-Cheng Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Generating models for integrated circuits with sensitivity-based mi...
- Patent number 8,122,406
- Issue date Feb 21, 2012
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Bing J. Sheu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ultra low area overhead retention flip-flop for power-down applicat...
- Patent number 7,639,056
- Issue date Dec 29, 2009
- Texas Instruments Incorporated
- Sumanth Katte Gururajarao
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Integrated circuit with dynamically controlled voltage supply
- Patent number 7,519,925
- Issue date Apr 14, 2009
- Texas Instruments Incorporated
- Sami Issa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for read-only memory
- Patent number 7,466,578
- Issue date Dec 16, 2008
- Texas Instruments Incorporated
- David B. Scott
- G11 - INFORMATION STORAGE
Information Patent Grant
N+ poly on high-k dielectric for semiconductor devices
- Patent number 7,407,850
- Issue date Aug 5, 2008
- Texas Instruments Incorporated
- Ramesh Venugopal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fast access memory architecture
- Patent number 7,376,038
- Issue date May 20, 2008
- Texas Instruments Incorporated
- Sudha Thiruvengadam
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive voltage control and body bias for performance and energy o...
- Patent number 7,307,471
- Issue date Dec 11, 2007
- Texas Instruments Incorporated
- Gordon Gammie
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for IDDQ measurement in system on a chip (SOC) de...
- Patent number 7,282,905
- Issue date Oct 16, 2007
- Texas Instruments Incorporated
- Wei Chen
- G01 - MEASURING TESTING
Information Patent Grant
Area efficient implementation of small blocks in an SRAM array
- Patent number 7,236,396
- Issue date Jun 26, 2007
- Texas Instruments Incorporated
- Theodore W. Houston
- G11 - INFORMATION STORAGE
Information Patent Grant
Design method and system for optimum performance in integrated circ...
- Patent number 7,216,310
- Issue date May 8, 2007
- Texas Instruments Incorporated
- Amitava Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switch structure for reduced voltage fluctuation in power domains a...
- Patent number 7,180,208
- Issue date Feb 20, 2007
- Texas Instruments Incorporated
- Wei Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated header switch with low-leakage PMOS and high-leakage NMO...
- Patent number 7,164,291
- Issue date Jan 16, 2007
- Texas Instruments Incorporated
- Hugh T. Mair
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit dynamic parameter management in response to dyna...
- Patent number 7,162,652
- Issue date Jan 9, 2007
- Texas Instruments Incorporated
- Sami Issa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retention register for system-transparent state retention
- Patent number 7,091,766
- Issue date Aug 15, 2006
- Texas Instruments Incorporated
- Uming Ko
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Retention register with normal functionality independent of retenti...
- Patent number 6,989,702
- Issue date Jan 24, 2006
- Texas Instruments Incorporated
- Uming Ko
- G11 - INFORMATION STORAGE
Information Patent Grant
Leakage current reduction method
- Patent number 6,956,398
- Issue date Oct 18, 2005
- Texas Instruments Incorporated
- Hugh Mair
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transistor circuit with varying resistance lightly doped diffused r...
- Patent number 6,831,337
- Issue date Dec 14, 2004
- Texas Instruments Incorporated
- Zhiqiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell with transistors having relatively high threshold volta...
- Patent number 6,773,972
- Issue date Aug 10, 2004
- Texas Instruments Incorporated
- Andrew Marshall
- G11 - INFORMATION STORAGE
Information Patent Grant
Transistor circuit with varying resistance lightly doped diffused r...
- Patent number 6,730,582
- Issue date May 4, 2004
- Texas Instruments Incorporated
- Zhiqiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having power supply voltage routed through sub...
- Patent number 6,727,578
- Issue date Apr 27, 2004
- Texas Instruments Incorporated
- David B. Scott
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced standby power memory array and method
- Patent number 6,678,202
- Issue date Jan 13, 2004
- Texas Instruments Incorporated
- David B. Scott
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of forming a metal oxide semiconductor transistor with self-...
- Patent number 6,620,692
- Issue date Sep 16, 2003
- Texas Instruments Incorporated
- David B. Scott
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Row decoder with switched power supply
- Patent number 6,426,655
- Issue date Jul 30, 2002
- Texas Instruments Incorporated
- Stewart M. DeSoto
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR LATCH-UP PREVENTION
- Publication number 20240386180
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Chia Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR LATCH-UP PREVENTION
- Publication number 20230237237
- Publication date Jul 27, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Chia Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR LATCH-UP PREVENTION
- Publication number 20210117605
- Publication date Apr 22, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Chia Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CIRCUITS HAVING A DIODE-CONNECTED TRANSISTOR WITH BACK-BIASE...
- Publication number 20130188416
- Publication date Jul 25, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Steven SWEI
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF
- Publication number 20130130456
- Publication date May 23, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chung-Cheng WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Adaptive Content-aware Aging Simulations
- Publication number 20120123745
- Publication date May 17, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Bing Jay Sheu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ENERGY HARVEST FROM AMBIENT SOURCES
- Publication number 20120032518
- Publication date Feb 9, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ming-Chieh HUANG
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF
- Publication number 20110291197
- Publication date Dec 1, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chung-Cheng WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CIRCUITS HAVING A DIODE-CONNECTED TRANSISTOR WITH BACK-BIASE...
- Publication number 20110267880
- Publication date Nov 3, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Steven SWEI
- G11 - INFORMATION STORAGE
Information Patent Application
WIDE-RANGE QUICK TUNABLE TRANSISTOR MODEL
- Publication number 20110153055
- Publication date Jun 23, 2011
- Taiwan Semiconductor Manufacturing Co., LTD
- Bing J. Sheu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Standard Cells Having Flexible Layout Architecture/Boundaries
- Publication number 20100269081
- Publication date Oct 21, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Chin Hou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generating Models for Integrated Circuits with Sensitivity-Based Mi...
- Publication number 20100106469
- Publication date Apr 29, 2010
- Bing J. Sheu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, DEVICE AND SYSTEM FOR CONFIGURING A STATIC RANDOM ACCESS ME...
- Publication number 20090046519
- Publication date Feb 19, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Alice Wang
- G11 - INFORMATION STORAGE
Information Patent Application
N+ POLY ON HIGH-K DIELECTRIC FOR SEMICONDUCTOR DEVICES
- Publication number 20080272442
- Publication date Nov 6, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Ramesh Venugopal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and systems for read-only memory
- Publication number 20080123388
- Publication date May 29, 2008
- TEXAS INSTRUMENTS INCORPORATED
- David B. Scott
- G11 - INFORMATION STORAGE
Information Patent Application
Fast access memory architecture
- Publication number 20070223294
- Publication date Sep 27, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Sudha Thiruvengadam
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Header Switch with Low-Leakage PMOS and High-Leakage NMO...
- Publication number 20070120578
- Publication date May 31, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Hugh T. Mair
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adaptive voltage control and body bias for performance an energy op...
- Publication number 20070046362
- Publication date Mar 1, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Gordon Gammie
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Area efficient implementation of small blocks in an SRAM array
- Publication number 20070002617
- Publication date Jan 4, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Theodore W. Houston
- G11 - INFORMATION STORAGE
Information Patent Application
Ultra low area overhead retention flip-flop for power-down applicat...
- Publication number 20060267654
- Publication date Nov 30, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Sumanth Katte Gururajarao
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
N+ poly on high-k dielectric for semiconductor devices
- Publication number 20060223248
- Publication date Oct 5, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Ramesh Venugopal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and method for IDDQ measurement in system on a chip (SOC) de...
- Publication number 20060125470
- Publication date Jun 15, 2006
- Wei Chen
- G01 - MEASURING TESTING
Information Patent Application
Integrated header switch with low-leakage PMOS and high-leakage NMO...
- Publication number 20060033525
- Publication date Feb 16, 2006
- Hugh T. Mair
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated circuit with dynamically controlled voltage supply
- Publication number 20050273742
- Publication date Dec 8, 2005
- TEXAS INSTRUMENTS INCORPORATED
- Sami Issa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEAKAGE CURRENT REDUCTION METHOD
- Publication number 20050212554
- Publication date Sep 29, 2005
- Hugh Mair
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Design method and system for optimum performance in integrated circ...
- Publication number 20050149887
- Publication date Jul 7, 2005
- TEXAS INSTRUMENTS INCORPORATED
- Amitava Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Switch structure for reduced voltage fluctuation in power domains a...
- Publication number 20050146228
- Publication date Jul 7, 2005
- Wei Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit dynamic parameter management in response to dyna...
- Publication number 20040260958
- Publication date Dec 23, 2004
- Sami Issa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Retention register with normal functionality independent of retenti...
- Publication number 20040051574
- Publication date Mar 18, 2004
- Uming Ko
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Transistor circuit with varying resistance lightly doped diffused r...
- Publication number 20040014293
- Publication date Jan 22, 2004
- Zhiqiang Wu
- H01 - BASIC ELECTRIC ELEMENTS

David Scott

Person

Patents Grantslast 30 patents

Method and system for latch-up prevention

Integrated circuits and manufacturing methods thereof

Memory circuits having a diode-connected transistor with back-biase...

Standard cells having flexible layout architecture/boundaries

Method and apparatus for energy harvest from ambient sources

Memory circuits having a diode-connected transistor with back-biase...

Integrated circuits and manufacturing methods thereof

Generating models for integrated circuits with sensitivity-based mi...

Ultra low area overhead retention flip-flop for power-down applicat...

Integrated circuit with dynamically controlled voltage supply

Methods and systems for read-only memory

N+ poly on high-k dielectric for semiconductor devices

Fast access memory architecture

Adaptive voltage control and body bias for performance and energy o...

System and method for IDDQ measurement in system on a chip (SOC) de...

Area efficient implementation of small blocks in an SRAM array

Design method and system for optimum performance in integrated circ...

Switch structure for reduced voltage fluctuation in power domains a...

Integrated header switch with low-leakage PMOS and high-leakage NMO...

Integrated circuit dynamic parameter management in response to dyna...

Retention register for system-transparent state retention

Retention register with normal functionality independent of retenti...

Leakage current reduction method

Transistor circuit with varying resistance lightly doped diffused r...

Memory cell with transistors having relatively high threshold volta...

Transistor circuit with varying resistance lightly doped diffused r...

Semiconductor device having power supply voltage routed through sub...

Reduced standby power memory array and method

Method of forming a metal oxide semiconductor transistor with self-...

Row decoder with switched power supply

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR LATCH-UP PREVENTION

METHOD AND SYSTEM FOR LATCH-UP PREVENTION

METHOD AND SYSTEM FOR LATCH-UP PREVENTION

MEMORY CIRCUITS HAVING A DIODE-CONNECTED TRANSISTOR WITH BACK-BIASE...

INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF

Adaptive Content-aware Aging Simulations

METHOD AND APPARATUS FOR ENERGY HARVEST FROM AMBIENT SOURCES

INTEGRATED CIRCUITS AND MANUFACTURING METHODS THEREOF

MEMORY CIRCUITS HAVING A DIODE-CONNECTED TRANSISTOR WITH BACK-BIASE...

WIDE-RANGE QUICK TUNABLE TRANSISTOR MODEL

Standard Cells Having Flexible Layout Architecture/Boundaries

Generating Models for Integrated Circuits with Sensitivity-Based Mi...

METHOD, DEVICE AND SYSTEM FOR CONFIGURING A STATIC RANDOM ACCESS ME...

N+ POLY ON HIGH-K DIELECTRIC FOR SEMICONDUCTOR DEVICES

Methods and systems for read-only memory

Fast access memory architecture

Integrated Header Switch with Low-Leakage PMOS and High-Leakage NMO...

Adaptive voltage control and body bias for performance an energy op...

Area efficient implementation of small blocks in an SRAM array

Ultra low area overhead retention flip-flop for power-down applicat...

N+ poly on high-k dielectric for semiconductor devices

System and method for IDDQ measurement in system on a chip (SOC) de...

Integrated header switch with low-leakage PMOS and high-leakage NMO...

Integrated circuit with dynamically controlled voltage supply

LEAKAGE CURRENT REDUCTION METHOD

Design method and system for optimum performance in integrated circ...

Switch structure for reduced voltage fluctuation in power domains a...

Integrated circuit dynamic parameter management in response to dyna...

Retention register with normal functionality independent of retenti...

Transistor circuit with varying resistance lightly doped diffused r...