David W. Daniel

Person

Divide, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Process independent alignment marks
- Patent number 7,095,483
- Issue date Aug 22, 2006
- LSI Logic Corporation
- David W. Daniel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process independent alignment marks
- Patent number 6,856,029
- Issue date Feb 15, 2005
- LSI Logic Corporation
- David W. Daniel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Anti-corrosion system
- Patent number 6,506,684
- Issue date Jan 14, 2003
- LSI Logic Corporation
- David W. Daniel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sonic assisted strengthening of gate oxides
- Patent number 6,372,520
- Issue date Apr 16, 2002
- LSI Logic Corporation
- Kang-Jay Hsia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Subtractive oxidation method of fabricating a short-length and vert...
- Patent number 6,355,532
- Issue date Mar 12, 2002
- LSI Logic Corporation
- John J. Seliskar
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method and apparatus for detecting a planarized outer layer of a se...
- Patent number 6,354,908
- Issue date Mar 12, 2002
- LSI Logic Corp.
- Derryl D. J. Allman
- B24 - GRINDING POLISHING
Information Patent Grant
MeV implantation to form vertically modulated N+ buried lay...
- Patent number 6,316,817
- Issue date Nov 13, 2001
- LSI Logic Corporation
- John J. Seliskar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for detecting a polishing endpoint based upon...
- Patent number 6,241,847
- Issue date Jun 5, 2001
- LSI Logic Corporation
- Derryl D. J. Allman
- B24 - GRINDING POLISHING
Information Patent Grant
Fabrication of differential gate oxide thicknesses on a single inte...
- Patent number 6,235,590
- Issue date May 22, 2001
- LSI Logic Corporation
- David W. Daniel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for detecting a planarized outer layer of a se...
- Patent number 6,201,253
- Issue date Mar 13, 2001
- LSI Logic Corporation
- Derryl D. J. Allman
- B24 - GRINDING POLISHING
Information Patent Grant
Apparatus and method of detecting a polishing endpoint layer of a s...
- Patent number 6,121,147
- Issue date Sep 19, 2000
- LSI Logic Corporation
- David W. Daniel
- B24 - GRINDING POLISHING
Information Patent Grant
Method for improved gate oxide integrity on bulk silicon
- Patent number 6,096,625
- Issue date Aug 1, 2000
- LSI Logic Corporation
- David W. Daniel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for detecting a polishing endpoint based upon...
- Patent number 6,077,783
- Issue date Jun 20, 2000
- LSI Logic Corporation
- Derryl D. J. Allman
- B24 - GRINDING POLISHING
Information Patent Grant
Reduction of silicon defect induced failures as a result of implant...
- Patent number 6,069,048
- Issue date May 30, 2000
- LSI Logic Corporation
- David W. Daniel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a low trigger voltage silicon controlled rec...
- Patent number 5,966,599
- Issue date Oct 12, 1999
- LSI Logic Corporation
- John D. Walker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of MEV implantation to form vertically modulated N+ buried laye...
- Patent number 5,858,828
- Issue date Jan 12, 1999
- Symbios, Inc.
- John J. Seliskar
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Process independent alignment marks
- Publication number 20050078289
- Publication date Apr 14, 2005
- LSI Logic Corporation
- David W. Daniel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for detecting a planarized outer layer of a se...
- Publication number 20010021622
- Publication date Sep 13, 2001
- Derryl D.J. Allman
- B24 - GRINDING POLISHING

David W. Daniel

Person

Patents Grantslast 30 patents

Process independent alignment marks

Process independent alignment marks

Anti-corrosion system

Sonic assisted strengthening of gate oxides

Subtractive oxidation method of fabricating a short-length and vert...

Method and apparatus for detecting a planarized outer layer of a se...

MeV implantation to form vertically modulated N&#x0002B; buried lay...

Method and apparatus for detecting a polishing endpoint based upon...

Fabrication of differential gate oxide thicknesses on a single inte...

Method and apparatus for detecting a planarized outer layer of a se...

Apparatus and method of detecting a polishing endpoint layer of a s...

Method for improved gate oxide integrity on bulk silicon

Method and apparatus for detecting a polishing endpoint based upon...

Reduction of silicon defect induced failures as a result of implant...

Method for fabricating a low trigger voltage silicon controlled rec...

Use of MEV implantation to form vertically modulated N+ buried laye...

Patents Applicationslast 30 patents

Process independent alignment marks

Method and apparatus for detecting a planarized outer layer of a se...

MeV implantation to form vertically modulated N+ buried lay...