Der-Min Yuan

Person

New Taipei City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method for testing semiconductor die pad untouched by probe and rel...
- Patent number 10,634,713
- Issue date Apr 28, 2020
- Piecemakers Technology, Inc.
- Der-Min Yuan
- G01 - MEASURING TESTING
Information Patent Grant
Immediate response low dropout regulation system and operation meth...
- Patent number 9,310,816
- Issue date Apr 12, 2016
- Etron Technology, Inc.
- Yen-An Chang
- G05 - CONTROLLING REGULATING
Information Patent Grant
Memory access circuit for double data/single data rate applications
- Patent number 9,019,776
- Issue date Apr 28, 2015
- Etron Technology, Inc.
- Chih-Huei Hu
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay lock loop system with a self-tracking function and method the...
- Patent number 8,432,206
- Issue date Apr 30, 2013
- Etron Technology, Inc.
- Der-Min Yuan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory having a disabling circuit and method for disabling the memory
- Patent number 8,345,500
- Issue date Jan 1, 2013
- Etron Technology, Inc.
- Shih-Hsing Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage regulator for memory
- Patent number 8,284,628
- Issue date Oct 9, 2012
- Etron Technology, Inc.
- Chun-Ching Hsia
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of reducing current of memory in self-refreshing mode and re...
- Patent number 8,228,751
- Issue date Jul 24, 2012
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip testing circuit
- Patent number 8,169,228
- Issue date May 1, 2012
- Etron Technology, Inc.
- Der-Min Yuan
- G01 - MEASURING TESTING
Information Patent Grant
Method of reducing current of memory in self-refreshing mode and re...
- Patent number 8,154,940
- Issue date Apr 10, 2012
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
System in package integrated circuit with self-generating reference...
- Patent number 8,125,838
- Issue date Feb 28, 2012
- Etron Technology, Inc.
- Shih-Hsing Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Data detecting apparatus and methods thereof
- Patent number 7,983,102
- Issue date Jul 19, 2011
- Etron Technology, Inc.
- Shih-Hsing Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Data flow scheme for low power DRAM
- Patent number 7,978,525
- Issue date Jul 12, 2011
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip testing circuit
- Patent number 7,940,588
- Issue date May 10, 2011
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Data flow scheme for low power DRAM
- Patent number 7,924,641
- Issue date Apr 12, 2011
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of reducing current of memory in self-refreshing mode and re...
- Patent number 7,843,754
- Issue date Nov 30, 2010
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory row architecture having memory row redundancy repair function
- Patent number 7,663,949
- Issue date Feb 16, 2010
- Etron Technology, Inc.
- Shih-Hsing Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic device and related method for performing compensation op...
- Patent number 7,576,597
- Issue date Aug 18, 2009
- Etron Technology, Inc.
- Yen-An Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Test patterns to insure read signal integrity for high speed DDR DRAM
- Patent number 7,370,250
- Issue date May 6, 2008
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Data flow scheme for low power DRAM
- Patent number 7,359,265
- Issue date Apr 15, 2008
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple power supplies for the driving circuit of local word line...
- Patent number 7,277,315
- Issue date Oct 2, 2007
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of data flow control for a high speed memory
- Patent number 7,184,341
- Issue date Feb 27, 2007
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable self-time scheme for write recovery by low speed tester
- Patent number 6,934,899
- Issue date Aug 23, 2005
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient data compression circuit for memory testing
- Patent number 6,543,015
- Issue date Apr 1, 2003
- Etron Technology, Inc.
- Gyh-Bin Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
DDR DRAM data coherence scheme
- Patent number 6,453,381
- Issue date Sep 17, 2002
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT
- Publication number 20240112707
- Publication date Apr 4, 2024
- ETRON TECHNOLOGY, INC.
- Der-Min Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT
- Publication number 20210217451
- Publication date Jul 15, 2021
- ETRON TECHNOLOGY, INC.
- Der-Min Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR TESTING SEMICONDUCTOR DIE PAD UNTOUCHED BY PROBE AND REL...
- Publication number 20190257879
- Publication date Aug 22, 2019
- Piecemakers Technology, Inc.
- Der-Min Yuan
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT
- Publication number 20190035440
- Publication date Jan 31, 2019
- ETRON TECHNOLOGY, INC.
- Der-Min Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT
- Publication number 20140025879
- Publication date Jan 23, 2014
- Der-Min Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMMEDIATE RESPONSE LOW DROPOUT REGULATION SYSTEM AND OPERATION METH...
- Publication number 20130234684
- Publication date Sep 12, 2013
- ETRON TECHNOLOGY, INC.
- Yen-An Chang
- G05 - CONTROLLING REGULATING
Information Patent Application
MEMORY ACCESS CIRCUIT FOR DOUBLE DATA/SINGLE DATA RATE APPLICATIONS
- Publication number 20130064018
- Publication date Mar 14, 2013
- Chih-Huei Hu
- G11 - INFORMATION STORAGE
Information Patent Application
DELAY LOCK LOOP SYSTEM WITH A SELF-TRACKING FUNCTION AND METHOD THE...
- Publication number 20120256666
- Publication date Oct 11, 2012
- Der-Min Yuan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage Regulator for Memory
- Publication number 20120063254
- Publication date Mar 15, 2012
- Chun-Ching Hsia
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY HAVING A DISABLING CIRCUIT AND METHOD FOR DISABLING THE MEMORY
- Publication number 20110176381
- Publication date Jul 21, 2011
- Shih-Hsing Wang
- G11 - INFORMATION STORAGE
Information Patent Application
Chip Testing Circuit
- Publication number 20110156742
- Publication date Jun 30, 2011
- Der-Min Yuan
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM IN PACKAGE INTEGRATED CIRCUIT WITH SELF-GENERATING REFERENCE...
- Publication number 20110085388
- Publication date Apr 14, 2011
- Shih-Hsing Wang
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RE...
- Publication number 20110026352
- Publication date Feb 3, 2011
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RE...
- Publication number 20110026351
- Publication date Feb 3, 2011
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
CHIP TESTING CIRCUIT
- Publication number 20100171509
- Publication date Jul 8, 2010
- Der-Min YUAN
- G01 - MEASURING TESTING
Information Patent Application
DATA DETECTING APPARATUS AND METHODS THEREOF
- Publication number 20100103753
- Publication date Apr 29, 2010
- Shih-Hsing WANG
- G11 - INFORMATION STORAGE
Information Patent Application
Power switch for transmitting a power source of low voltage between...
- Publication number 20100026372
- Publication date Feb 4, 2010
- Yen-An Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RE...
- Publication number 20090154277
- Publication date Jun 18, 2009
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ROW ARCHITECTURE HAVING MEMORY ROW REDUNDANCY REPAIR FUNCTION
- Publication number 20080316845
- Publication date Dec 25, 2008
- Shih-Hsing Wang
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC DEVICE AND RELATED METHOD FOR PERFORMING COMPENSATION OP...
- Publication number 20080303559
- Publication date Dec 11, 2008
- Yen-An Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data flow scheme for low power DRAM
- Publication number 20080219071
- Publication date Sep 11, 2008
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
Data flow scheme for low power DRAM
- Publication number 20080181028
- Publication date Jul 31, 2008
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
Sense amplifier-based latch
- Publication number 20080048727
- Publication date Feb 28, 2008
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
Fuse circuit for repair and detection
- Publication number 20070268062
- Publication date Nov 22, 2007
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
Data flow scheme for low power DRAM
- Publication number 20070153600
- Publication date Jul 5, 2007
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
Test patterns to insure read signal integrity for high speed DDR DRAM
- Publication number 20070143649
- Publication date Jun 21, 2007
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
Multiple power supplies for the driving circuit of local word line...
- Publication number 20070133317
- Publication date Jun 14, 2007
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
Method of data flow control for a high speed memory
- Publication number 20060039231
- Publication date Feb 23, 2006
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE
Information Patent Application
High area efficient data line architecture
- Publication number 20030206479
- Publication date Nov 6, 2003
- Chun Shiah
- G11 - INFORMATION STORAGE
Information Patent Application
Variable self-time scheme for write recovery by low speed tester
- Publication number 20030145260
- Publication date Jul 31, 2003
- Etron Technology, Inc.
- Der-Min Yuan
- G11 - INFORMATION STORAGE

Der-Min Yuan

Person

Patents Grantslast 30 patents

Method for testing semiconductor die pad untouched by probe and rel...

Immediate response low dropout regulation system and operation meth...

Memory access circuit for double data/single data rate applications

Delay lock loop system with a self-tracking function and method the...

Memory having a disabling circuit and method for disabling the memory

Voltage regulator for memory

Method of reducing current of memory in self-refreshing mode and re...

Chip testing circuit

Method of reducing current of memory in self-refreshing mode and re...

System in package integrated circuit with self-generating reference...

Data detecting apparatus and methods thereof

Data flow scheme for low power DRAM

Chip testing circuit

Data flow scheme for low power DRAM

Method of reducing current of memory in self-refreshing mode and re...

Memory row architecture having memory row redundancy repair function

Electronic device and related method for performing compensation op...

Test patterns to insure read signal integrity for high speed DDR DRAM

Data flow scheme for low power DRAM

Multiple power supplies for the driving circuit of local word line...

Method of data flow control for a high speed memory

Variable self-time scheme for write recovery by low speed tester

Efficient data compression circuit for memory testing

DDR DRAM data coherence scheme

Patents Applicationslast 30 patents

DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT

DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT

METHOD FOR TESTING SEMICONDUCTOR DIE PAD UNTOUCHED BY PROBE AND REL...

DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT

DYNAMIC RANDOM ACCESS MEMORY APPLIED TO AN EMBEDDED DISPLAY PORT

IMMEDIATE RESPONSE LOW DROPOUT REGULATION SYSTEM AND OPERATION METH...

MEMORY ACCESS CIRCUIT FOR DOUBLE DATA/SINGLE DATA RATE APPLICATIONS

DELAY LOCK LOOP SYSTEM WITH A SELF-TRACKING FUNCTION AND METHOD THE...

Voltage Regulator for Memory

MEMORY HAVING A DISABLING CIRCUIT AND METHOD FOR DISABLING THE MEMORY

Chip Testing Circuit

SYSTEM IN PACKAGE INTEGRATED CIRCUIT WITH SELF-GENERATING REFERENCE...

METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RE...

METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RE...

CHIP TESTING CIRCUIT

DATA DETECTING APPARATUS AND METHODS THEREOF

Power switch for transmitting a power source of low voltage between...

METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RE...

MEMORY ROW ARCHITECTURE HAVING MEMORY ROW REDUNDANCY REPAIR FUNCTION

ELECTRONIC DEVICE AND RELATED METHOD FOR PERFORMING COMPENSATION OP...

Data flow scheme for low power DRAM

Data flow scheme for low power DRAM

Sense amplifier-based latch

Fuse circuit for repair and detection

Data flow scheme for low power DRAM

Test patterns to insure read signal integrity for high speed DDR DRAM

Multiple power supplies for the driving circuit of local word line...

Method of data flow control for a high speed memory

High area efficient data line architecture

Variable self-time scheme for write recovery by low speed tester