BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:
FIG. 1 shows a simplified data-path schematic diagram from a memory cell to a data line sense amplifier according to a conventional dynamic random access memory (DRAM) architecture.
FIG. 2 is a timing diagram of operations of a conventional MDQSA.
FIG. 3 is a schematic diagram according to an embodiment of the invention.
FIG. 4 is a timing diagram according to the invention.
FIG. 5 is a detailed diagram of the sense amplifier shown in FIG. 3.
DETAILED DESCRIPTION OF THE INVENTION
The sense amplifier-based latch of the invention will be described with reference to the accompanying drawings.
FIG. 3 is a schematic diagram according to an embodiment of the invention. FIG. 4 is a timing diagram according to the invention.
Referring to FIG. 3, according to an embodiment of the invention, a sense amplifier-based latch 300, applicable to ordinary DRAM circuits, comprises an input circuit 340, a sense amplifier 310, a latch circuit 320 and an output circuit 330. The input circuit 340 comprises a plurality of identical input units 341˜34N (N≧1, N is a positive integer), each of which receives both a master data line signal (MDQ1˜MDQN) and a complementary master data line signal (MDQ1B˜MDQNB) in response to a data isolation signal (SAISO1˜SAISON). Meanwhile, there is one single data isolation signal corresponding to one of the input units 341˜34N is enabled (SAISO is at a low voltage level as shown in FIG. 4) in each period of time such that the master data line signal and the complementary master data line signal previously received by the enabled input unit are then outputted as the input signal DQ and the complementary input signal DQB (not shown).
The latch circuit 320 is used to latch voltage levels of an amplified signal DT_DLSA and a complementary amplified signal DTB_DLSA and then generate an output signal DT and a complementary output signal DTB. In this embodiment, the latch circuit 320, which is implemented with two NAND gates 321, 322, is a typical S-R latch. Alternatively, the latch circuit 320 can be implemented with two NOR gates as well. However, the latch circuit is not limited to either two NAND gates or two NOR gates but includes other configurations, as the latch circuit may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein.
The output circuit 330 comprises two NOT gates 331, 332, a NAND gate 333, a NOR gate 334, a PMOS transistor Mp11 and a NMOS transistor MN4. The output circuit 330 is responsive to a control signal SOENB. While being at a low voltage level, the control signal SOENB is inverted to a high voltage level right away. That allows both the output signal DT (i.e., the amplified input signal DQ) to pass through the NAND gate 333 and the complementary output signal DTB (i.e., the complementary amplified input signal DQB) to pass through the NOT gate 331 and the NOR gate 334. Then, the voltage level of the output signal DT is able to be correctly delivered to an I/O data bus via a node A after the PMOS transistor Mp11 and the NMOS transistor MN4 are switched on.
In response to two control signals MDQPUB, SAEN, the sense amplifier 310 amplifies the input signal DQ and the complementary input signal DQB and then generates the amplified signal DT_DLSA and the complementary amplified signal DTB_DLSA. Hereinafter, the operations of the sense amplifier 310 will be detailed as follows.
FIG. 5 is a detailed diagram of the sense amplifier shown in FIG. 3.
The sense amplifier 310 comprises a pre-charge circuit 512 and an amplifier circuit 514. In response to the control signal MDQPUB, the pre-charge circuit 512, comprising three PMOS transistors Mp5, Mp6, Mp8, is used to pre-charge voltage levels of the amplified signal DT_DLSA and the complementary amplified signal DTB_DLSA to a pre-defined voltage level (such as Vdd) before receiving the input signal DQ and the complementary input signal DQB. With respect to the circuit architecture, sources of transistors Mp5, Mp6 are connected to an operating voltage Vdd while the drain of a transistor Mp6 and the source of a transistor Mp8 are connected to receive the complementary input signal DQB. Drains of transistors Mp5, Mp8 receive the input signal DQ while gates of three PMOS transistors Mp5, Mp6, Mp8 are connected to each other in response to the control signal MDQPUB. Referring back to FIG. 4, while the control signal MDQPUB is at a low voltage level, three PMOS transistors Mp5, Mp6, Mp8 are simultaneously switched on, thereby pre-charging both the amplified signal DT_DLSA and the complementary amplified signal DTB_DLSA to a pre-defined voltage level Vdd. It should be noted that there is no charge consumption in other circuits while the pre-charge circuit 512 is pre-charging.
On the other hand, the amplifier circuit 514 is simultaneously responsive to two control signals MDQPUB, SAEN. As shown in FIG. 4, while control signals MDQPUB, SAEN are at a high voltage level, the amplifier circuit 514 is used to amplify voltage levels of the input signal DQ and the complementary input signal DQB and then generate the amplified signal DT_DLSA and the complementary amplified signal DTB_DLSA. According to the embodiment, the amplifier circuit 514 is a cross-coupled sense amplifier, comprising three PMOS transistors Mp7, Mp9, Mp10 and three NMOS transistors MN1, MN2, MN3. With respect to the circuit architecture, sources of transistors Mp7, Mp9 are connected to the operating voltage Vdd while the source of the transistor MN3 is grounded. Drains of transistors Mp10, MN3 and sources of transistors MN1, MN2 are connected to each other. Drains of transistors Mp9, MN1 and gates of transistors MN1, MN2 are connected to receive the complementary input signal DQB while drains of transistors Mp7, MN2 and gates of transistors Mp9, MN1 are connected to receive the input signal DQ. The transistors Mp10, MN3 are responsive to the control signals MDQPUB, SAEN, respectively. As shown in FIG. 4, while the control signals MDQPUB, SAEN are at a high voltage level, an imperceptible voltage difference between two complemented signals DQ, DQB is amplified by the amplifier circuit 514 such that the resultant voltage difference between the amplified signal DT_DLSA and the complementary amplified signal DTB_DLSA is enlarged.
Comparing two respective waveforms of two complemented signals DT/DTB shown in FIG. 2 and FIG. 4, it is obvious that the variation frequency of two complemented signals DT/DTB shown in FIG. 4 is lower than that of two complemented signals DT/DTB shown in FIG. 2. The voltage levels of two complemented signals DT/DTB shown in FIG. 4 remain fixed except that the data contained in two complemented signals DT/DTB change. This is one advantage of the invention which results from employing the latch circuit 320. Referring to FIG. 4, there is no voltage variation in the waveforms of two complemented signals DT/DTB while the next data contained in the output signal DT is equal to the previous data (e.g., equal to 1) contained in the output signal DT The sense amplifier 310 has no additional charge consumption except to perform the sense and the pre-charge operations. Therefore, the invention reduces a lot of charge consumption as well as glitches and malfunctions for memory circuits.
On the other hand, since the interval data_window of two complemented signals DT/DTB shown in FIG. 4 is much longer, the corresponding data contained in the output signal DT/DTB is able to be fetched easily and correctly by a control circuit without an additional hardwired control. In summary, the invention is not only compatible to the pipelining transmission characteristic of DRAM circuits, but also accelerates the data transfer rate of data paths, thus suitable for high-speed circuit applications.
While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention should not be limited to the specific construction and arrangement shown and described, since various other modifications may occur to those ordinarily skilled in the art.
Patent Application
20080048727
