Derick J. Wristers

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
SOI semiconductor device having enhanced, self-aligned dielectric r...
- Patent number 7,544,999
- Issue date Jun 9, 2009
- Advanced Micro Devices, Inc.
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistors with controllable threshold voltages, and various metho...
- Patent number 7,432,136
- Issue date Oct 7, 2008
- Advanced Micro Devices, Inc.
- Mark B. Fuselier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained-silicon device with different silicon thicknesses
- Patent number 7,417,250
- Issue date Aug 26, 2008
- Advanced Micro Devices, Inc.
- James F. Buller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming doped regions in the bulk substrate of an SOI sub...
- Patent number 7,335,568
- Issue date Feb 26, 2008
- Advanced Micro Devices, Inc.
- Derick J. Wristers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective P-channel VT adjustment in SiGe system for leakage optimi...
- Patent number 7,253,045
- Issue date Aug 7, 2007
- Advanced Micro Devices, Inc.
- Derick J. Wristers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor component
- Patent number 7,208,383
- Issue date Apr 24, 2007
- Advanced Micro Devices, Inc.
- Chad Weintraub
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Biased, triple-well fully depleted SOI structure
- Patent number 7,180,136
- Issue date Feb 20, 2007
- Advanced Micro Devices, Inc.
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming doped regions in the bulk substrate of an SOI sub...
- Patent number 7,129,142
- Issue date Oct 31, 2006
- Advanced Micro Devices, Inc.
- Derick J. Wristers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation structure having implanted silicon atoms at the top corne...
- Patent number 6,979,878
- Issue date Dec 27, 2005
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite spacer liner for improved transistor performance
- Patent number 6,949,436
- Issue date Sep 27, 2005
- Advanced Micro Devices, Inc.
- James F. Buller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained-silicon devices with different silicon thicknesses
- Patent number 6,936,506
- Issue date Aug 30, 2005
- Advanced Micro Devices, Inc.
- James F. Buller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Biased, triple-well fully depleted SOI structure, and various metho...
- Patent number 6,919,236
- Issue date Jul 19, 2005
- Advanced Micro Devices, Inc.
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making an SOI semiconductor device having enhanced, self-...
- Patent number 6,884,702
- Issue date Apr 26, 2005
- Advanced Micro Devices, Inc.
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully-depleted SOI device
- Patent number 6,876,037
- Issue date Apr 5, 2005
- Advanced Micro Devices, Inc.
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor component having an early...
- Patent number 6,833,307
- Issue date Dec 21, 2004
- Advanced Micro Devices, Inc.
- Derick Wristers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Linewidth measurement structure with embedded scatterometry structure
- Patent number 6,822,260
- Issue date Nov 23, 2004
- Advanced Micro Devices, Inc.
- Hormuzdiar E. Nariman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polysilicon linewidth measurement structure with embedded transistor
- Patent number 6,812,506
- Issue date Nov 2, 2004
- Advanced Micro Devices, Inc.
- Hormuzdiar E. Nariman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ring oscillator with embedded scatterometry grate array
- Patent number 6,801,096
- Issue date Oct 5, 2004
- Advanced Micro Devices, Inc.
- Hormuzdiar E. Nariman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Doping methods for fully-depleted SOI structures, and device compri...
- Patent number 6,780,686
- Issue date Aug 24, 2004
- Advanced Micro Devices, Inc.
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Narrow width CMOS devices fabricated on strained lattice semiconduc...
- Patent number 6,764,908
- Issue date Jul 20, 2004
- Advanced Micro Devices, Inc.
- Daniel Kadosh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device formed over a multiple thickness buried oxide...
- Patent number 6,737,332
- Issue date May 18, 2004
- Advanced Micro Devices, Inc.
- Mark B. Fuselier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically programmed MOS transistor source/drain series resistance
- Patent number 6,727,534
- Issue date Apr 27, 2004
- Advanced Micro Devices, Inc.
- James F. Buller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of ultra-shallow depth source/drain extensions for MOS tr...
- Patent number 6,727,136
- Issue date Apr 27, 2004
- Advanced Micro Devices, Inc.
- James F. Buller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with tensile strain silicon introduced by comp...
- Patent number 6,707,106
- Issue date Mar 16, 2004
- Advanced Micro Devices, Inc.
- Derick J. Wristers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low temperature solid-phase epitaxy fabrication process for MOS dev...
- Patent number 6,689,671
- Issue date Feb 10, 2004
- Advanced Micro Devices, Inc.
- Bin Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure having elevated salicided source/drain regi...
- Patent number 6,674,135
- Issue date Jan 6, 2004
- Advanced Micro Devices, Inc.
- Jon Cheek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tri-level segmented control transistor and fabrication method
- Patent number 6,661,057
- Issue date Dec 9, 2003
- Robert Dawson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure having a metal gate electrode and elevated...
- Patent number 6,638,829
- Issue date Oct 28, 2003
- Advanced Micro Devices, Inc.
- Jon Cheek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tilted counter-doped implant to sharpen halo profile
- Patent number 6,589,847
- Issue date Jul 8, 2003
- Advanced Micro Devices, Inc.
- Daniel Kadosh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor device having an enhanced width dimension and a method o...
- Patent number 6,580,122
- Issue date Jun 17, 2003
- Advanced Micro Devices, Inc.
- Derick J. Wristers
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF FORMING DOPED REGIONS IN THE BULK SUBSTRATE OF AN SOI SUB...
- Publication number 20070015322
- Publication date Jan 18, 2007
- Advanced Micro Devices, Inc.
- Derick J. Wristers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Biased, triple-well fully depleted SOI structure
- Publication number 20050184341
- Publication date Aug 25, 2005
- Advanced Micro Devices, Inc.
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOI semiconductor device having enhanced, self-aligned dielectric r...
- Publication number 20050151133
- Publication date Jul 14, 2005
- Advanced Micro Devices, Inc.
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Composite spacer liner for improved transistor performance
- Publication number 20040259343
- Publication date Dec 23, 2004
- Advanced Micro Devices, Inc.
- James F. Buller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device formed over a multiple thickness buried oxide...
- Publication number 20040219761
- Publication date Nov 4, 2004
- Advanced Micro Devices, Inc.
- Mark B. Fuselier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Doping methods for fully-depleted SOI structures, and device compri...
- Publication number 20040169227
- Publication date Sep 2, 2004
- Advanced Micro Devices, Inc.
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor component and method of manufacture
- Publication number 20040087094
- Publication date May 6, 2004
- Advanced Micro Devices, Inc.
- Derick Wristers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming doped regions in the bulk substrate of an SOI sub...
- Publication number 20030228722
- Publication date Dec 11, 2003
- Derick J. Wristers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of making an soi semiconductor device having enhanced, self-...
- Publication number 20030223258
- Publication date Dec 4, 2003
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transistors with controllable threshold voltages, and various metho...
- Publication number 20030207504
- Publication date Nov 6, 2003
- Mark B. Fuselier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOPING METHODS FOR FULLY-DEPLETED SOI STRUCTURES, AND DEVICE COMPRI...
- Publication number 20030178678
- Publication date Sep 25, 2003
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Biased, triple-well fully depleted SOI structure, and various metho...
- Publication number 20030178622
- Publication date Sep 25, 2003
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOPANT DIFFUSION-RETARDING BARRIER REGION FORMED WITHIN POLYSILICON...
- Publication number 20020004294
- Publication date Jan 10, 2002
- MARK I. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IGFET WITH SILICIDE CONTACT ON ULTRA-THIN GATE
- Publication number 20020003273
- Publication date Jan 10, 2002
- ROBERT DAWSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING AN IGFET USING SOLID PHASE DIFFUSION TO DOPE THE G...
- Publication number 20010039094
- Publication date Nov 8, 2001
- DERICK J. WRISTERS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY MEMORY CELL ASSEMBLY AND METHODS
- Publication number 20010020716
- Publication date Sep 13, 2001
- MARK I. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS

Derick J. Wristers

Person

Patents Grantslast 30 patents

SOI semiconductor device having enhanced, self-aligned dielectric r...

Transistors with controllable threshold voltages, and various metho...

Strained-silicon device with different silicon thicknesses

Method of forming doped regions in the bulk substrate of an SOI sub...

Selective P-channel VT adjustment in SiGe system for leakage optimi...

Method of manufacturing a semiconductor component

Biased, triple-well fully depleted SOI structure

Method of forming doped regions in the bulk substrate of an SOI sub...

Isolation structure having implanted silicon atoms at the top corne...

Composite spacer liner for improved transistor performance

Strained-silicon devices with different silicon thicknesses

Biased, triple-well fully depleted SOI structure, and various metho...

Method of making an SOI semiconductor device having enhanced, self-...

Fully-depleted SOI device

Method for manufacturing a semiconductor component having an early...

Linewidth measurement structure with embedded scatterometry structure

Polysilicon linewidth measurement structure with embedded transistor

Ring oscillator with embedded scatterometry grate array

Doping methods for fully-depleted SOI structures, and device compri...

Narrow width CMOS devices fabricated on strained lattice semiconduc...

Semiconductor device formed over a multiple thickness buried oxide...

Electrically programmed MOS transistor source/drain series resistance

Formation of ultra-shallow depth source/drain extensions for MOS tr...

Semiconductor device with tensile strain silicon introduced by comp...

Low temperature solid-phase epitaxy fabrication process for MOS dev...

Semiconductor structure having elevated salicided source/drain regi...

Tri-level segmented control transistor and fabrication method

Semiconductor structure having a metal gate electrode and elevated...

Tilted counter-doped implant to sharpen halo profile

Transistor device having an enhanced width dimension and a method o...

Patents Applicationslast 30 patents

METHOD OF FORMING DOPED REGIONS IN THE BULK SUBSTRATE OF AN SOI SUB...

Biased, triple-well fully depleted SOI structure

SOI semiconductor device having enhanced, self-aligned dielectric r...

Composite spacer liner for improved transistor performance

Semiconductor device formed over a multiple thickness buried oxide...

Doping methods for fully-depleted SOI structures, and device compri...

Semiconductor component and method of manufacture

Method of forming doped regions in the bulk substrate of an SOI sub...

Method of making an soi semiconductor device having enhanced, self-...

Transistors with controllable threshold voltages, and various metho...

DOPING METHODS FOR FULLY-DEPLETED SOI STRUCTURES, AND DEVICE COMPRI...

Biased, triple-well fully depleted SOI structure, and various metho...

DOPANT DIFFUSION-RETARDING BARRIER REGION FORMED WITHIN POLYSILICON...

IGFET WITH SILICIDE CONTACT ON ULTRA-THIN GATE

METHOD OF MAKING AN IGFET USING SOLID PHASE DIFFUSION TO DOPE THE G...

HIGH DENSITY MEMORY CELL ASSEMBLY AND METHODS