Ding-Ming Kwai

Person

Hsinchu County, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Power source tolerance analysis method and system
- Patent number 10,564,706
- Issue date Feb 18, 2020
- Industrial Technology Research Institute
- Chang-Tzu Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of yield prejudgment and bump re-assignment and computer rea...
- Patent number 10,339,253
- Issue date Jul 2, 2019
- Industrial Technology Research Institute
- Chi-Han Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for generating power distribution network (PDN) model, and p...
- Patent number 10,289,141
- Issue date May 14, 2019
- Industrial Technology Research Institute
- Chang-Tzu Lin
- G05 - CONTROLLING REGULATING
Information Patent Grant
Memory controlling method and memory system
- Patent number 9,905,277
- Issue date Feb 27, 2018
- Industrial Technology Research Institute
- Pei-Wen Luo
- G11 - INFORMATION STORAGE
Information Patent Grant
Fault-tolerance through silicon via interface and controlling metho...
- Patent number 9,588,717
- Issue date Mar 7, 2017
- Industrial Technology Research Institute
- Chih-Yen Lo
- G11 - INFORMATION STORAGE
Information Patent Grant
3-D memory and built-in self-test circuit thereof
- Patent number 9,406,401
- Issue date Aug 2, 2016
- Industrial Technology Research Institute
- Chih-Yen Lo
- G11 - INFORMATION STORAGE
Information Patent Grant
Test method for interposer
- Patent number 9,347,981
- Issue date May 24, 2016
- Industrial Technology Research Institute
- Yung-Fa Chou
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method for generating a power delivery network
- Patent number 9,183,345
- Issue date Nov 10, 2015
- Industrial Technology Research Institute
- Chang-Tzu Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device
- Patent number 9,064,549
- Issue date Jun 23, 2015
- Industrial Technology Research Institute
- Yung-Fa Chou
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device stacked structure
- Patent number 9,048,342
- Issue date Jun 2, 2015
- Industrial Technology Research Institute
- Ding-Ming Kwai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for testing through-silicon-via
- Patent number 8,937,486
- Issue date Jan 20, 2015
- National Tsing Hua University
- Cheng-Wen Wu
- G01 - MEASURING TESTING
Information Patent Grant
Operating method of hardwired switch
- Patent number 8,912,015
- Issue date Dec 16, 2014
- Industrial Technology Research Institute
- Ting-Sheng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technology of memory repair after stacking of three-dimensional int...
- Patent number 8,854,853
- Issue date Oct 7, 2014
- Industrial Technology Research Institute
- Yung-Fa Chou
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked structure and stacked method for three-dimensional chip
- Patent number 8,710,676
- Issue date Apr 29, 2014
- Industrial Technology Research Institute
- Yung-Fa Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus of an integrated circuit
- Patent number 8,689,160
- Issue date Apr 1, 2014
- Industrial Technology Research Institute
- Chang Tzu Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for repairing an integrated circuit
- Patent number 8,683,276
- Issue date Mar 25, 2014
- Industrial Technology Research Institute
- Yung-Fa Chou
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for testing through-silicon-via and the circuit thereof
- Patent number 8,531,199
- Issue date Sep 10, 2013
- National Tsing Hua University
- Cheng Wen Wu
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus of an integrated circuit
- Patent number 8,522,186
- Issue date Aug 27, 2013
- Industrial Technology Research Institute
- Chang Tzu Lin
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Wafer and method for improving yield rate of wafer
- Patent number 8,384,201
- Issue date Feb 26, 2013
- Industrial Technology Research Institute
- Ting-Sheng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked structure of chips
- Patent number 8,344,520
- Issue date Jan 1, 2013
- Industrial Technology Research Institute
- Yung-Fa Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hardwired switch of die stack and operating method of hardwired switch
- Patent number 8,217,521
- Issue date Jul 10, 2012
- Industrial Technology Research Institute
- Ting-Sheng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of chip repair by stacking a plurality of bad dies
- Patent number 8,193,006
- Issue date Jun 5, 2012
- Industrial Technology Research Institute
- Yung-Fa Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die stacking structure and fabricating method thereof
- Patent number 8,026,585
- Issue date Sep 27, 2011
- Industrial Technology Research Institute
- Yung-Fa Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation circuit
- Patent number 7,924,083
- Issue date Apr 12, 2011
- Industrial Technology Research Institute
- Yung-Fa Chou
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF YIELD PREJUDGMENT AND BUMP RE-ASSIGNMENT AND COMPUTER REA...
- Publication number 20190121930
- Publication date Apr 25, 2019
- Industrial Technology Research Institute
- Chi-Han Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER SOURCE TOLERANCE ANALYSIS METHOD AND SYSTEM
- Publication number 20180157314
- Publication date Jun 7, 2018
- Industrial Technology Research Institute
- Chang-Tzu Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR GENERATING POWER DISTRIBUTION NETWORK (PDN) MODEL, AND P...
- Publication number 20170023961
- Publication date Jan 26, 2017
- Industrial Technology Research Institute
- Chang-Tzu LIN
- G05 - CONTROLLING REGULATING
Information Patent Application
MEMORY CONTROLLING METHOD AND MEMORY SYSTEM
- Publication number 20170003908
- Publication date Jan 5, 2017
- Industrial Technology Research Institute
- Pei-Wen LUO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT-TOLERANCE THROUGH SILICON VIA INTERFACE AND CONTROLLING METHO...
- Publication number 20160132403
- Publication date May 12, 2016
- Industrial Technology Research Institute
- Chih-Yen Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR GENERATING A POWER DELIVERY NETWORK
- Publication number 20150199467
- Publication date Jul 16, 2015
- Industrial Technology Research Institute
- Chang-Tzu LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE
- Publication number 20150049569
- Publication date Feb 19, 2015
- Industrial Technology Research Institute
- Yung-Fa Chou
- G11 - INFORMATION STORAGE
Information Patent Application
HYBRID ERROR CORRECTION METHOD AND MEMORY REPAIR APPARATUS THEREOF
- Publication number 20140325311
- Publication date Oct 30, 2014
- Industrial Technology Research Institute
- Chih-Yen Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST METHOD FOR INTERPOSER
- Publication number 20140139259
- Publication date May 22, 2014
- Industrial Technology Research Institute
- Yung-Fa Chou
- G01 - MEASURING TESTING
Information Patent Application
3-D Memory and Built-In Self-Test Circuit Thereof
- Publication number 20130326294
- Publication date Dec 5, 2013
- Industrial Technology Research Institute
- Chih-Yen Lo
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR TESTING THROUGH-SILICON-VIA
- Publication number 20130293255
- Publication date Nov 7, 2013
- Cheng-Wen Wu
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS OF AN INTEGRATED CIRCUIT
- Publication number 20130283224
- Publication date Oct 24, 2013
- CHANG TZU LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus And Method For Repairing An Integrated Circuit
- Publication number 20130210170
- Publication date Aug 15, 2013
- INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Yung-Fa CHOU
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE STACKED STRUCTURE
- Publication number 20130161819
- Publication date Jun 27, 2013
- Industrial Technology Research Institute
- Ding-Ming Kwai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS OF AN INTEGRATED CIRCUIT
- Publication number 20130159950
- Publication date Jun 20, 2013
- Industrial Technology Research Institute
- CHANG TZU LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGY OF MEMORY REPAIR AFTER STACKING OF THREE-DIMENSIONAL INT...
- Publication number 20130064026
- Publication date Mar 14, 2013
- Industrial Technology Research Institute
- Yung-Fa Chou
- G11 - INFORMATION STORAGE
Information Patent Application
OPERATING METHOD OF HARDWIRED SWITCH
- Publication number 20120231563
- Publication date Sep 13, 2012
- Industrial Technology Research Institute
- Ting-Sheng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED STRUCTURE OF CHIPS
- Publication number 20120193815
- Publication date Aug 2, 2012
- Industrial Technology Research Institute
- Yung-Fa Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED STRUCTURE AND STACKED METHOD FOR THREE-DIMENSIONAL CHIP
- Publication number 20120146207
- Publication date Jun 14, 2012
- Industrial Technology Research Institute
- Yung-Fa Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMAGE CAPTURE DEVICE
- Publication number 20120133807
- Publication date May 31, 2012
- INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Cheng-Wen Wu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ELECTROSTATIC DISCHARGE PROTECTION SCHEME FOR SEMICONDUCTOR DEVICE...
- Publication number 20110304010
- Publication date Dec 15, 2011
- Industrial Technology Research Institute
- Zhe-Wei Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF
- Publication number 20110080185
- Publication date Apr 7, 2011
- National Tsing Hua University
- CHENG WEN WU
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF
- Publication number 20110080184
- Publication date Apr 7, 2011
- National Tsing Hua University
- CHENG WEN WU
- G01 - MEASURING TESTING
Information Patent Application
ISOLATION CIRCUIT
- Publication number 20110006829
- Publication date Jan 13, 2011
- Industrial Technology Research Institute
- Yung-Fa Chou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
WAFER AND METHOD FOR IMPROVING YIELD RATE OF WAFER
- Publication number 20100320565
- Publication date Dec 23, 2010
- Industrial Technology Research Institute
- Ting-Sheng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REPAIRING CHIP AND STACKED STRUCTURE OF CHIPS
- Publication number 20100295189
- Publication date Nov 25, 2010
- Industrial Technology Research Institute
- Yung-Fa Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HARDWIRED SWITCH OF DIE STACK AND OPERATING METHOD OF HARDWIRED SWITCH
- Publication number 20100289139
- Publication date Nov 18, 2010
- Industrial Technology Research Institute
- Ting-Sheng Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYOUT STRUCTURE AND METHOD OF DIE
- Publication number 20100244220
- Publication date Sep 30, 2010
- Industrial Technology Research Institute
- Yung-Fa Chou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low-power reading reference circuit for split-gate flash memory
- Publication number 20070133275
- Publication date Jun 14, 2007
- Intellectual Property Libarary Company
- Meng-Fan Chang
- G11 - INFORMATION STORAGE

Ding-Ming Kwai

Person

Patents Grantslast 30 patents

Power source tolerance analysis method and system

Method of yield prejudgment and bump re-assignment and computer rea...

Method for generating power distribution network (PDN) model, and p...

Memory controlling method and memory system

Fault-tolerance through silicon via interface and controlling metho...

3-D memory and built-in self-test circuit thereof

Test method for interposer

Apparatus and method for generating a power delivery network

Memory device

Semiconductor device stacked structure

Method for testing through-silicon-via

Operating method of hardwired switch

Technology of memory repair after stacking of three-dimensional int...

Stacked structure and stacked method for three-dimensional chip

Method and apparatus of an integrated circuit

Apparatus and method for repairing an integrated circuit

Method for testing through-silicon-via and the circuit thereof

Method and apparatus of an integrated circuit

Wafer and method for improving yield rate of wafer

Stacked structure of chips

Hardwired switch of die stack and operating method of hardwired switch

Method of chip repair by stacking a plurality of bad dies

Die stacking structure and fabricating method thereof

Isolation circuit

Patents Applicationslast 30 patents

METHOD OF YIELD PREJUDGMENT AND BUMP RE-ASSIGNMENT AND COMPUTER REA...

POWER SOURCE TOLERANCE ANALYSIS METHOD AND SYSTEM

METHOD FOR GENERATING POWER DISTRIBUTION NETWORK (PDN) MODEL, AND P...

MEMORY CONTROLLING METHOD AND MEMORY SYSTEM

FAULT-TOLERANCE THROUGH SILICON VIA INTERFACE AND CONTROLLING METHO...

APPARATUS AND METHOD FOR GENERATING A POWER DELIVERY NETWORK

MEMORY DEVICE

HYBRID ERROR CORRECTION METHOD AND MEMORY REPAIR APPARATUS THEREOF

TEST METHOD FOR INTERPOSER

3-D Memory and Built-In Self-Test Circuit Thereof

METHOD FOR TESTING THROUGH-SILICON-VIA

METHOD AND APPARATUS OF AN INTEGRATED CIRCUIT

Apparatus And Method For Repairing An Integrated Circuit

SEMICONDUCTOR DEVICE STACKED STRUCTURE

METHOD AND APPARATUS OF AN INTEGRATED CIRCUIT

TECHNOLOGY OF MEMORY REPAIR AFTER STACKING OF THREE-DIMENSIONAL INT...

OPERATING METHOD OF HARDWIRED SWITCH

STACKED STRUCTURE OF CHIPS

STACKED STRUCTURE AND STACKED METHOD FOR THREE-DIMENSIONAL CHIP

IMAGE CAPTURE DEVICE

ELECTROSTATIC DISCHARGE PROTECTION SCHEME FOR SEMICONDUCTOR DEVICE...

METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF

METHOD FOR TESTING THROUGH-SILICON-VIA AND THE CIRCUIT THEREOF

ISOLATION CIRCUIT

WAFER AND METHOD FOR IMPROVING YIELD RATE OF WAFER

METHOD FOR REPAIRING CHIP AND STACKED STRUCTURE OF CHIPS

HARDWIRED SWITCH OF DIE STACK AND OPERATING METHOD OF HARDWIRED SWITCH

LAYOUT STRUCTURE AND METHOD OF DIE

Low-power reading reference circuit for split-gate flash memory