Donald S. Gerber

Person

Scottsdale, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of programming an array of NMOS EEPROM cells that minimizes...
- Patent number 8,094,503
- Issue date Jan 10, 2012
- Microchip Technology Incorporated
- Jeffrey A. Shields
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for programming and erasing an array of NMOS EEPROM cells th...
- Patent number 7,817,474
- Issue date Oct 19, 2010
- Microchip Technology Incorporated
- Jeffrey A. Shields
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for programming and erasing an array of NMOS EEPROM cells th...
- Patent number 7,466,591
- Issue date Dec 16, 2008
- Microchip Technology Incorporated
- Jeffrey A. Shields
- G11 - INFORMATION STORAGE
Information Patent Grant
Independently programmable memory segments within a PMOS electrical...
- Patent number 6,504,191
- Issue date Jan 7, 2003
- Microchip Technology Incorporated
- Donald S. Gerber
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for independent threshold voltage control of m...
- Patent number 6,432,761
- Issue date Aug 13, 2002
- Microchip Technology Incorporated
- Don Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell having an ONO film with an ONO sidewall and method of f...
- Patent number 6,432,773
- Issue date Aug 13, 2002
- Microchip Technology Incorporated
- Donald S. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Independently programmable memory segments within a PMOS electrical...
- Patent number 6,300,183
- Issue date Oct 9, 2001
- Microchip Technology Incorporated
- Donald S. Gerber
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming method for a memory cell
- Patent number 6,236,595
- Issue date May 22, 2001
- Microchip Technology Incorporated
- Donald S. Gerber
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for minimizing program disturb in a memory cell
- Patent number 6,222,761
- Issue date Apr 24, 2001
- Microchip Technology Incorporated
- Donald S. Gerber
- G11 - INFORMATION STORAGE
Information Patent Grant
Means and methods of lifting and relocating an epitaxial device layer
- Patent number 5,073,230
- Issue date Dec 17, 1991
- Arizona Board of Regents acting on behalf of Arizona State University
- George N. Maracas
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF PROGRAMMING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZES...
- Publication number 20100302857
- Publication date Dec 2, 2010
- MICROCHIP TECHNOLOGY INCORPORATED
- Jeffrey A. Shields
- G11 - INFORMATION STORAGE
Information Patent Application
Method for Programming and Erasing an Array of NMOS EEPROM Cells th...
- Publication number 20090122618
- Publication date May 14, 2009
- MICROCHIP TECHNOLOGY INCORPORATED
- Jeffrey A. Shields
- G11 - INFORMATION STORAGE
Information Patent Application
Method for Programming and Erasing an Array of NMOS EEPROM Cells Th...
- Publication number 20070280001
- Publication date Dec 6, 2007
- MICROCHIP TECHNOLOGY INCORPORATED
- Jeffrey A. Shields
- G11 - INFORMATION STORAGE
Information Patent Application
Independently programmable memory segments within an NMOS electrica...
- Publication number 20070140008
- Publication date Jun 21, 2007
- MICROCHIP TECHNOLOGY INCORPORATED
- Jeffrey Shields
- G11 - INFORMATION STORAGE
Information Patent Application
Independently programmable memory segments within a PMOS electrical...
- Publication number 20020014642
- Publication date Feb 7, 2002
- Donald S. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for minimizing program disturb in a memory cell
- Publication number 20020006059
- Publication date Jan 17, 2002
- Donald S. Gerber
- G11 - INFORMATION STORAGE

Donald S. Gerber

Person

Patents Grantslast 30 patents

Method of programming an array of NMOS EEPROM cells that minimizes...

Method for programming and erasing an array of NMOS EEPROM cells th...

Method for programming and erasing an array of NMOS EEPROM cells th...

Independently programmable memory segments within a PMOS electrical...

Apparatus and method for independent threshold voltage control of m...

Memory cell having an ONO film with an ONO sidewall and method of f...

Independently programmable memory segments within a PMOS electrical...

Programming method for a memory cell

Method for minimizing program disturb in a memory cell

Means and methods of lifting and relocating an epitaxial device layer

Patents Applicationslast 30 patents

METHOD OF PROGRAMMING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZES...

Method for Programming and Erasing an Array of NMOS EEPROM Cells th...

Method for Programming and Erasing an Array of NMOS EEPROM Cells Th...

Independently programmable memory segments within an NMOS electrica...

Independently programmable memory segments within a PMOS electrical...

Method for minimizing program disturb in a memory cell