Douglas M. Reber

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Plated pillar dies having integrated electromagnetic shield layers
- Patent number 11,694,970
- Issue date Jul 4, 2023
- NXP B.V.
- Douglas Michael Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor manufacturing using disposable test circuitry within...
- Patent number 10,553,508
- Issue date Feb 4, 2020
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with embedded capacitor and methods of manufa...
- Patent number 10,522,615
- Issue date Dec 31, 2019
- NXP USA, INC.
- Sergio A. Ajuria
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post contact air gap formation
- Patent number 10,510,616
- Issue date Dec 17, 2019
- NXP USA, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming inter-level dielectric structures on semiconducto...
- Patent number 10,262,893
- Issue date Apr 16, 2019
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with graphene encapsulated metal and method th...
- Patent number 10,204,860
- Issue date Feb 12, 2019
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multigate transistor
- Patent number 10,103,241
- Issue date Oct 16, 2018
- NXP USA, INC.
- Douglas Michael Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate contacts for a transistor
- Patent number 10,038,081
- Issue date Jul 31, 2018
- NXP USA, INC.
- Douglas Michael Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for placing stressors within an integrated cir...
- Patent number 10,014,257
- Issue date Jul 3, 2018
- NXP USA, INC.
- Douglas M. Reber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solar cell powered integrated circuit device and method therefor
- Patent number 10,008,447
- Issue date Jun 26, 2018
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for verifying design rule checks
- Patent number 9,934,349
- Issue date Apr 3, 2018
- NXP USA, INC.
- Inder Mohan Bhawnani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of forming inter-level dielectric structures on semiconducto...
- Patent number 9,818,642
- Issue date Nov 14, 2017
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fuse/resistor utilizing interconnect and vias and method of making
- Patent number 9,685,405
- Issue date Jun 20, 2017
- NXP USA, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit design using pre-marked circuit element object l...
- Patent number 9,652,577
- Issue date May 16, 2017
- NXP USA, INC.
- Edward O. Travis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device with graphene encapsulated metal and method th...
- Patent number 9,640,430
- Issue date May 2, 2017
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor manufacturing for forming bond pads and seal rings
- Patent number 9,601,354
- Issue date Mar 21, 2017
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with embedded capacitor and methods of manufa...
- Patent number 9,548,266
- Issue date Jan 17, 2017
- NXP USA, INC.
- Sergio A. Ajuria
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D device packaging using through-substrate posts
- Patent number 9,515,006
- Issue date Dec 6, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D device packaging using through-substrate pillars
- Patent number 9,508,701
- Issue date Nov 29, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D device packaging using through-substrate posts
- Patent number 9,508,702
- Issue date Nov 29, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Though-substrate vias (TSVs) and method therefor
- Patent number 9,466,569
- Issue date Oct 11, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for placing stressors on interconnects within...
- Patent number 9,455,220
- Issue date Sep 27, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capping layer interface interruption for stress migration mitigation
- Patent number 9,443,804
- Issue date Sep 13, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Teleconferencing environment having auditory and visual cues
- Patent number 9,445,050
- Issue date Sep 13, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Edward O. Travis
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Grant
Integrated circuit heater for reducing stress in the integrated cir...
- Patent number 9,318,409
- Issue date Apr 19, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with embedded heat spreading
- Patent number 9,245,817
- Issue date Jan 26, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Edward O. Travis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin beam deposited fuse
- Patent number 9,236,344
- Issue date Jan 12, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a nanotube layer and method for forming
- Patent number 9,224,692
- Issue date Dec 29, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress migration mitigation utilizing induced stress effects in met...
- Patent number 9,142,507
- Issue date Sep 22, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a packaged semiconductor device
- Patent number 9,134,366
- Issue date Sep 15, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Sergio A. Ajuria
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
PLATED PILLAR DIES HAVING INTEGRATED ELECTROMAGNETIC SHIELD LAYERS
- Publication number 20220302042
- Publication date Sep 22, 2022
- NXP B.V.
- Douglas Michael Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POST CONTACT AIR GAP FORMATION
- Publication number 20190206740
- Publication date Jul 4, 2019
- NXP USA, Inc.
- Mehul D. SHROFF
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIGATE TRANSISTOR
- Publication number 20180261682
- Publication date Sep 13, 2018
- NXP USA, Inc.
- Douglas Michael REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING INTER-LEVEL DIELECTRIC STRUCTURES ON SEMICONDUCTO...
- Publication number 20180047616
- Publication date Feb 15, 2018
- NXP USA INC.
- DOUGLAS M. REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH GRAPHENE ENCAPSULATED METAL AND METHOD TH...
- Publication number 20170194264
- Publication date Jul 6, 2017
- NXP USA, Inc.
- DOUGLAS M. REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH GRAPHENE ENCAPSULATED METAL AND METHOD TH...
- Publication number 20170084484
- Publication date Mar 23, 2017
- FREESCALE SEMICONDUCTOR, INC.
- DOUGLAS M. REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFA...
- Publication number 20170084682
- Publication date Mar 23, 2017
- NXP USA, Inc.
- SERGIO A. AJURIA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHOD FOR PLACING STRESSORS WITHIN AN INTEGRATED CIR...
- Publication number 20170069572
- Publication date Mar 9, 2017
- Freescale Semiconductor, Inc.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLAR CELL POWERED INTEGRATED CIRCUIT DEVICE AND METHOD THEREFOR
- Publication number 20160343696
- Publication date Nov 24, 2016
- FREESCALE SEMICONDUCTOR, INC.
- DOUGLAS M. REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING INTER-LEVEL DIELECTRIC STRUCTURES ON SEMICONDUCTO...
- Publication number 20160307791
- Publication date Oct 20, 2016
- FREESCALE SEMICONDUCTOR, INC.
- DOUGLAS M. REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR VERIFYING DESIGN RULE CHECKS
- Publication number 20160283642
- Publication date Sep 29, 2016
- FREESCALE SEMICONDUCTOR, INC.
- INDER MOHAN BHAWNANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TELECONFERENCING ENVIRONMENT HAVING AUDITORY AND VISUAL CUES
- Publication number 20160142674
- Publication date May 19, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Edward O. TRAVIS
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Application
THOUGH-SUBSTRATE VIAS (TSVs) AND METHOD THEREFOR
- Publication number 20160133574
- Publication date May 12, 2016
- FREESCALE SEMICONDUCTOR, INC.
- MEHUL D. SHROFF
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Design Using Pre-Marked Circuit Element Object L...
- Publication number 20160098510
- Publication date Apr 7, 2016
- Edward O. Travis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIR...
- Publication number 20160093549
- Publication date Mar 31, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFA...
- Publication number 20160064324
- Publication date Mar 3, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Sergio A. Ajuria
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR MANUFACTURING FOR FORMING BOND PADS AND SEAL RINGS
- Publication number 20160064294
- Publication date Mar 3, 2016
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHOD FOR PLACING STRESSORS WITHIN AN INTEGRATED CIR...
- Publication number 20150348898
- Publication date Dec 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- MEHUL D. SHROFF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRESS MIGRATION MITIGATION UTILIZING INDUCED STRESS EFFECTS IN MET...
- Publication number 20150249048
- Publication date Sep 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING A NANOTUBE LAYER AND METHOD FOR FORMING
- Publication number 20150206843
- Publication date Jul 23, 2015
- FREESCALE SEMICONDUCTOR, INC.
- DOUGLAS M. REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Manufacturing Using Disposable Test Circuitry Within...
- Publication number 20150200146
- Publication date Jul 16, 2015
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR MANUFACTURING USING DESIGN VERIFICATION WITH MARKERS
- Publication number 20150178438
- Publication date Jun 25, 2015
- ERTUGRUL DEMIRCAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Thin Beam Deposited Fuse
- Publication number 20150137311
- Publication date May 21, 2015
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D DEVICE PACKAGING USING THROUGH-SUBSTRATE PILLARS
- Publication number 20150091178
- Publication date Apr 2, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D DEVICE PACKAGING USING THROUGH-SUBSTRATE POSTS
- Publication number 20150091187
- Publication date Apr 2, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D DEVICE PACKAGING USING THROUGH-SUBSTRATE POSTS
- Publication number 20150091160
- Publication date Apr 2, 2015
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE
- Publication number 20150061709
- Publication date Mar 5, 2015
- Sergio A. Ajuria
- G01 - MEASURING TESTING
Information Patent Application
Capping Layer Interface Interruption for Stress Migration Mitigation
- Publication number 20150035151
- Publication date Feb 5, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stress Migration Mitigation
- Publication number 20150040092
- Publication date Feb 5, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSE/RESISTOR UTILIZING INTERCONNECT AND VIAS AND METHOD OF MAKING
- Publication number 20140353797
- Publication date Dec 4, 2014
- MEHUL D. SHROFF
- H01 - BASIC ELECTRIC ELEMENTS

Douglas M. Reber

Person

Patents Grantslast 30 patents

Plated pillar dies having integrated electromagnetic shield layers

Semiconductor manufacturing using disposable test circuitry within...

Semiconductor package with embedded capacitor and methods of manufa...

Post contact air gap formation

Method of forming inter-level dielectric structures on semiconducto...

Semiconductor device with graphene encapsulated metal and method th...

Multigate transistor

Substrate contacts for a transistor

Apparatus and method for placing stressors within an integrated cir...

Solar cell powered integrated circuit device and method therefor

Method for verifying design rule checks

Method of forming inter-level dielectric structures on semiconducto...

Fuse/resistor utilizing interconnect and vias and method of making

Integrated circuit design using pre-marked circuit element object l...

Semiconductor device with graphene encapsulated metal and method th...

Semiconductor manufacturing for forming bond pads and seal rings

Semiconductor package with embedded capacitor and methods of manufa...

3D device packaging using through-substrate posts

3D device packaging using through-substrate pillars

3D device packaging using through-substrate posts

Though-substrate vias (TSVs) and method therefor

Apparatus and method for placing stressors on interconnects within...

Capping layer interface interruption for stress migration mitigation

Teleconferencing environment having auditory and visual cues

Integrated circuit heater for reducing stress in the integrated cir...

Semiconductor device with embedded heat spreading

Thin beam deposited fuse

Semiconductor device having a nanotube layer and method for forming

Stress migration mitigation utilizing induced stress effects in met...

Method for forming a packaged semiconductor device

Patents Applicationslast 30 patents

PLATED PILLAR DIES HAVING INTEGRATED ELECTROMAGNETIC SHIELD LAYERS

POST CONTACT AIR GAP FORMATION

MULTIGATE TRANSISTOR

METHOD OF FORMING INTER-LEVEL DIELECTRIC STRUCTURES ON SEMICONDUCTO...

SEMICONDUCTOR DEVICE WITH GRAPHENE ENCAPSULATED METAL AND METHOD TH...

SEMICONDUCTOR DEVICE WITH GRAPHENE ENCAPSULATED METAL AND METHOD TH...

SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFA...

APPARATUS AND METHOD FOR PLACING STRESSORS WITHIN AN INTEGRATED CIR...

SOLAR CELL POWERED INTEGRATED CIRCUIT DEVICE AND METHOD THEREFOR

METHOD OF FORMING INTER-LEVEL DIELECTRIC STRUCTURES ON SEMICONDUCTO...

METHOD FOR VERIFYING DESIGN RULE CHECKS

TELECONFERENCING ENVIRONMENT HAVING AUDITORY AND VISUAL CUES

THOUGH-SUBSTRATE VIAS (TSVs) AND METHOD THEREFOR

Integrated Circuit Design Using Pre-Marked Circuit Element Object L...

INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIR...

SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFA...

SEMICONDUCTOR MANUFACTURING FOR FORMING BOND PADS AND SEAL RINGS

APPARATUS AND METHOD FOR PLACING STRESSORS WITHIN AN INTEGRATED CIR...

STRESS MIGRATION MITIGATION UTILIZING INDUCED STRESS EFFECTS IN MET...

SEMICONDUCTOR DEVICE HAVING A NANOTUBE LAYER AND METHOD FOR FORMING

Semiconductor Manufacturing Using Disposable Test Circuitry Within...

SEMICONDUCTOR MANUFACTURING USING DESIGN VERIFICATION WITH MARKERS

Thin Beam Deposited Fuse

3D DEVICE PACKAGING USING THROUGH-SUBSTRATE PILLARS

3D DEVICE PACKAGING USING THROUGH-SUBSTRATE POSTS

3D DEVICE PACKAGING USING THROUGH-SUBSTRATE POSTS

METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE

Capping Layer Interface Interruption for Stress Migration Mitigation

Stress Migration Mitigation

FUSE/RESISTOR UTILIZING INTERCONNECT AND VIAS AND METHOD OF MAKING