Patent Application
20250210463
This application claims priority under 35 U.S.C. § 119 to India patent application Ser. No. 20/234,1087415, filed Dec. 20, 2023 the contents of which are incorporated by reference herein.
Embodiments of the subject matter described herein relate to semiconductor-based integrated circuits and forming electrical interconnections within such circuits and between semiconductor die and other structures.
Semiconductor devices formed on or within individual semiconductor die include both electrical interconnections between devices on the same die as well as electrical interconnections tied to contact structures on top or bottom surfaces of a die that allow external devices to be coupled to the circuits formed on or within the semiconductor die.
In an example embodiment an electronic component includes a first semiconductor die having an upper surface, a lower surface, and a first volume of semiconductor material between the upper surface and the lower surface. Electronic devices are integrally formed in a first device region that forms part of the first volume of semiconductor material. The component further includes a first electrically-conductive buried interconnect formed within the first volume of semiconductor material between the first device region and the lower surface of the first semiconductor die. The buried interconnect extends from an interior portion of the first semiconductor die to a first edge of the first semiconductor die along a lateral direction that is parallel to the upper and lower surfaces of the first semiconductor die. The first edge extends between the upper surface and the lower surface of the first semiconductor die and the first buried interconnect is exposed at the first edge of the first semiconductor die.
In another example embodiment an electronic component includes a first semiconductor die having an upper surface, a lower surface, and a first volume of semiconductor material between the upper surface and the lower surface. Electronic devices integrally formed in a first device region that forms part of the first volume of semiconductor material. A first electrically-conductive buried interconnect is formed within the first volume of semiconductor material between the first device region and the lower surface of the first semiconductor die. The first buried interconnect extends along a lateral direction that is parallel to the upper and lower surfaces of the first semiconductor die; and the first buried interconnect is electrically coupled to one or more of the electronic devices of the first device region.
The present disclosure is illustrated by way of examples, embodiments and the like and is not limited by the accompanying figures, in which like reference numbers indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. The figures along with the detailed description are incorporated and form part of the specification and serve to further illustrate examples, embodiments and the like, and explain various principles and advantages, in accordance with the present disclosure, wherein:
The following detailed description provides examples for the purposes of understanding and is not intended to limit the invention or the application and uses of the same. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or the following detailed description.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements or regions in the figures may be exaggerated relative to other elements or regions to help improve understanding of embodiments of the invention.
The terms “first,” “second,” “third,” “fourth” and the like in the description and the claims, if any, may be used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have” and any variations thereof, are intended to cover non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner. As used herein the terms “substantial” and “substantially” mean sufficient to accomplish the stated purpose in a practical manner and that minor imperfections, if any, are not significant for the stated purpose.
Directional references such as “top,” “bottom,” “left,” “right,” “above,” “below,” and so forth, unless otherwise stated, are not intended to require any preferred orientation and are made with reference to the orientation of the corresponding figure or figures for purposes of illustration.
It will be appreciated that the steps of various processes described herein are non-limiting examples of suitable processes according to embodiments and are for the purposes of illustration. Embodiments herein may use any suitable processes including those that omit steps of example processes described herein, perform those steps or similar steps in different orders, and the like. It will also be appreciated that well-known techniques and features may be omitted for clarity.
Unless explicitly stated otherwise, the terms “approximately” and “substantially”, when used herein to refer to measurable quantities including, but not limited to dimensions, shall mean that a quantity is equal to a stated value or that two quantities are equal to each other to within an amount determined by accepted tolerances of the process(es) chosen to fabricate the relevant structure and/or an accepted measurement accuracy of the method(s) and/or measurement device(s) chosen to measure the dimensions or other properties described.
Conventional approaches to providing external contacts to devices formed on or within semiconductor die such as copper pillars or other structures which require through-substrate vias can have disadvantage. For example, through-substrate vias and related structures can cause mechanical stresses in surrounded portions of a die. These mechanical stresses can result in variations in device performance which can be difficult to predict or otherwise undesirable. As a result, it may be necessary to implement design rules to ensure that vias or other interconnect structures are kept away from transistors and other sensitive devices. But such approaches can increase the minimum footprint of a die leading to increased manufacturing costs, among other potential disadvantages.
Accordingly, embodiments described herein provide additional flexibility to route electrical interconnections within a semiconductor die using buried electrical interconnects that can run parallel the upper and lower surfaces of a semiconductor die which can reduce or eliminate the need for electrical interconnections that pass through a substrate in proximity to sensitive devices. Along these lines,
In one or more embodiments, a buried interconnect such as the buried interconnect 150 is surrounded by a dielectric material (not explicitly shown) that electrically isolates the buried interconnect from the semiconductor material of the substrate 105 that immediately surrounds it. A dielectric layer 120 (or multiple dielectric layers 120) can include electrically conductive buried interconnects 150 which extended horizontally and can be coupled to vias including through-substrate vias (“TSVs”) such as the TSV 135. The term TSV is used herein to refer to vias or similar structures which pass through all or part of a semiconductor substrate such as the substrate 105 and similar substrates, as described herein. Dielectric layers such as the dielectric layer(s) 120 disposed on a surface of a die that include electrical interconnections routed within them may be referred to as a redistribution layer, or “RDL” (or as multiple redistribution layers or “RDLs”), or one or more “build-up layers.” As shown in
In one or more embodiments, a semiconductor die includes a seal-ring structure such as the seal ring structure 140. In this example, the seal ring structure 140 can be formed together with structures such as horizontal interconnects such as the interconnect 130 and vertical interconnects such as the TSV 135 or the interconnect 137. A seal ring structure such as the seal ring 140 may form a continuous structure along the perimeter of a die such as the die 100. A structure such as the seal ring 140 need not be electrically coupled to any other structure and can be used to protect sensitive portions of a semiconductor die such as the die 100 (e.g., devices 115) from damage due to mechanical processes such as wafer dicing (i.e., singulating the die from a larger die or wafer) or chemical processes. As shown, a dielectric material 160 may be deposited or otherwise formed on the edge 112 and/or the lower surface 106 to electrically insulate the substrate 105. The dielectric material may be removed (or prevented from being formed) to expose a portion of the buried interconnect 150 at the edge 112. Any suitable material can be used for the dielectric material 160 including, but not limited, to polymeric materials, oxide materials, nitride materials, and so on.
In one or more such embodiments, a buried interconnect can pass underneath the seal ring structure such as the seal ring 140 as shown in
It will be appreciated that although
At step 210, dielectric material 160 is deposited or otherwise formed on the lower surface 106 of the substrate 105. It will be appreciated that the orientation of the substrate 105 is rotated relative to its orientation in
Next, at step 220 a suitably selective anisotropic etch is used to selective removed the semiconducting material of the substrate 105 at the bottom of the vertical shafts 212 (at the dashed line 213) which creates the enlarged cavities 222 below the dashed line 213, as shown. As one non-limiting example, when the substrate 105 is silicon and the dielectric material 160 is silicon nitride, a plasma etch process using sulfur hexafluoride (SF6) can be used to selectively and anisotropically etch the silicon to create the enlarged cavities. Subsequent annealing (e.g., in a hydrogen atmosphere) can be employed to cause the enlarged cavities to coalesce into a single cavity.
At step 230, a seed layer is deposited within the cavity (shown after the enlarged cavities have coalesced, now identified as the buried interconnect 150). For example, titanium nitride can be deposited by atomic layer deposition, followed by deposition of tungsten which fills the enlarged cavity and the vertical shafts 212. The metal in the vertical shafts above the cavity can be etched away using a suitably selective anisotropic etch and the holes in the bottom of each shaft 212 can then be plugged by forming tungsten nitride using an ammonia-based plasma process. A subsequent thermal oxidation process can seal the vertical shafts 212. It will be appreciated that in one or more embodiments vertical shafts such as the vertical shafts 212 are not sealed off and instead remain filled with metal.
At step 240, the cavity has been sealed as described above to form the buried interconnect 150. The positions of the vertical shafts 212 are indicated by dashed lines. As above, in one or more embodiments, the vertical shafts 212 can be left in the indicated positions and remain filled with metal or another suitable material. A portion of the TSV 135 can be formed using known techniques to form an electrical connection to the buried interconnect 150.
At step 250, devices 115 are formed within the semiconductor material of the substrate 105. Finally, at step 260 the dielectric layer(s) 120 is formed on the upper surface 107 of the substrate 105 and the interconnect 130 is formed, along with additional vertical structures such as the seal ring 140 and portions of the TSV 135 that extend into the dielectric material 120. At step 260 the substrate is also diced through the area indicated by dashed lines to singulate the die 100. In one or more embodiments, as shown in
It will be appreciated that the process 200 is a so-called front-end-of-line (FEOL) process in which the buried interconnect 150 and associated structures are formed first, followed by fabrication of the devices 115 within the die 100. In one or more embodiments, a buried interconnect such as the buried interconnect 150 and associated structures are formed after devices such as the devices 115 are formed. Accordingly,
The process 300 has steps 310, 320, 330, 340, 350, and 360 which are described in connection with fabrication of the die 100. It will be appreciated that in one or more embodiments, a die such as the die 100 is fabricated in a related process which may omit one or more steps of the process 300 or similar steps, perform steps of the process 300 or similar steps in a different order, or add steps not explicitly described in connection with the process 300. It will be further understood that well-known process steps may not be described and that multiple processing steps performed together or at different times may be described as part of a single step of the process 300 for ease of understanding.
At step 310, a dielectric material 390 has been deposited or otherwise formed on the lower surface 106 of the substrate 105 and patterned as shown. The dielectric material 160 (or other suitable masking material) is used as an etch mask for a suitable anisotropic etching process which forms the vertical shafts 312. Note that step 310 may be substantially similar to step 210 of the process 200 when performed with the substrate 105 oriented as shown.
Next, at step 320 a suitably selective anisotropic etch is used to selective removed the semiconducting material of the substrate 105 at the bottom of the vertical shafts 212 (at the dashed line 213) which creates the enlarged cavities 322 below the dotted line 313, as shown. As one non-limiting example, when the substrate 105 is silicon and the dielectric material 160 is silicon nitride, a plasma etch process using sulfur hexafluoride (SF6) can be used to selectively and anisotropically etch the silicon to create the enlarged cavities. Note that step 320 may be substantially similar to portions of step 220 of the process 200 when performed with the substrate 105 oriented as shown. At step 330, the enlarged cavities 322 are annealed (e.g., in a hydrogen atmosphere) to form a hollow cavity 332. The vertical shafts 312 are closed by selective oxidation (e.g., thermal oxidation of silicon). In one or more embodiments, residual nitride or other dielectric material is anisotropically etched to expose the sidewalls of the vertical shafts 312 before closing them via the oxidation process.
At step 340, devices 115 are formed within the semiconductor material of the substrate 105. At step 350, after formation of the devices 115, trenches corresponding to the location of one or more TSVs 135 are etched or otherwise formed using any suitable process(es) to expose portions of the hollow cavity 332. The trenches corresponding to the TSVs 135 can be metallized using any suitable processes and materials, including but not limited to known processes for forming metallized vias in semiconductor substrates and can use metals or other electrically conductive materials suitable for use in such processes including, as nonlimiting examples, cobalt, tungsten, copper, and heavily-doped polysilicon.
Finally, at step 360 the dielectric layer 120 (or dielectric layers 120) is formed on the upper surface 107 of the substrate 105 and the interconnect 130 is formed, along with additional vertical structures such as the seal ring 140 and portions of the TSV 135 that extend into the dielectric material 120. At step 360 the substrate 105 is also diced through the area indicated by dashed lines to singulate the die 100. In one or more embodiments, dicing the substrate 105 exposes the buried interconnect 150 at the edge 112 of the substrate 105.
It will be appreciated that the process 300 and similar processes can be particularly useful for various applications, such as the example die 500 of
At step 410, the larger substrate or die is diced to singulate the die 100 and expose the edge 112 of the substrate 105. Next, at step 420, dielectric material 460 (e.g., dielectric material 160) is deposited or otherwise formed on the edge 112 of the substrate 105 and optionally on the edge of the dielectric layer(s) 120 as shown. The dielectric material 460 can be any suitable material including, but not limited to, a polyimide film.
At step 430 a focused radiation source 499 (e.g., a laser or other suitable radiation source) is used to etch or drill through the dielectric material 460 and through the semiconductor material of the substrate 105 as indicate by the dashed lines until the TSV 135 is encountered, forming a bore hole 432. The bore hole 432 can then be lined with dielectric material such as an oxide, nitride, or other material (not shown).
Next at step 440, the bore hole 432 is filled with any suitably electrically conductive material using any suitable process to form the buried interconnect 150. For example, the bore hole 432 may be filled with a metal such as copper, tungsten, nickel, or the like. Additional conductive material 442 may be deposited onto the edge 112 of the substrate 105 to form a macroscopic or otherwise enlarged contact pad along the edge 112 of the substrate 105.
It will be understood that
The buried interconnects 750 (e.g., buried interconnects 150, 550, or 650; represented by the buried interconnects 750a, 750b) can each be coupled to external structures or devices. For example, the die 700 is shown mounted to a metallized structure 790 on a carrier substrate 795 (e.g., a printed circuit board or any other suitable carrier substrate). The metallized structure 790 may be part of (or coupled) to a voltage distribution node coupled to a supply voltage, a ground plane or other reference potential node, or to a signal source (e.g., a clock signal generator or any other signal source). As a result, circuit nodes or other structures of the die 700 can be easily coupled to a ground potential (or any circuit node or signal line). Notably, the arrangement pictured in
In one or more embodiments, as shown in
Die with buried interconnects according to embodiments herein can provide greater flexibility to assemble multiple die or other components into multichip packages. Along these lines
In the example of
Once secured to the carrier substrate 895, die such as the two die 800 can be directly coupled to each other via a volume of conductive material 875, which can be any suitable material. Thus in one or more embodiments, two die may be coupled together via a volume of conductive adhesive that bonds two buried interconnects together at respective edges of each die. Similarly, in one or more embodiments, two die may be coupled together via a volume of electrically conductive solder that bonds two buried interconnects together at respective edges of each die. In addition, in one or more embodiments, two die may be coupled together via a volume of electrically conductive sintered die attachment material that bonds two buried interconnects together at respective edges of each die.
It will be understood that embodiments herein related to the example of
Features of embodiments may be understood by way of one or more of the following examples:
Example 1: A device or method that includes a first semiconductor die having an upper surface, a lower surface, and a first volume of semiconductor material between the upper surface and the lower surface. Electronic devices integrally are formed in a first device region that forms part of the first volume of semiconductor material. A first electrically-conductive buried interconnect is formed within the first volume of semiconductor material between the first device region and the lower surface of the first semiconductor die and extends from an interior portion of the first semiconductor die toward a first edge of the first semiconductor die along a lateral direction that is parallel to the upper and lower surfaces of the first semiconductor die. The first edge extends between the upper surface and the lower surface of the first semiconductor die.
Example 2: The device or method of Example 1 that also includes an electrically-conductive first via that extends vertically through the first device region of the first volume of semiconductor material and is electrically coupled to the first buried interconnect within the first volume of semiconductor material.
Example 3: The device or method of Example 1 or Example 2 where the first buried interconnect is electrically coupled to one or more of the electronic devices of the first device region.
Example 4: The device or method of any of Examples 1-3 where the first via is formed of a first electrically-conductive material and the first buried interconnect is formed of a second electrically-conductive material.
Example 5: The device or method of any of Examples 1-4 that also includes: A metallic seal-ring structure formed on the upper surface of the first semiconductor die above the first volume of semiconductor material, where the metallic seal-ring structure surrounds a central portion of the upper surface of the first semiconductor die; where a portion of first the buried interconnect between the interior portion and the first edge of the first semiconductor die passes underneath the seal-ring structure.
Example 6: The device or method of any of Examples 1-5 that further includes a circuit substrate disposed next to the first semiconductor die that has an upper surface, a lower surface, and a first edge that extends between the upper surface and the lower surface of the circuit substrate; an electrical contact that is exposed at the first edge of the circuit substrate; and a volume of electrically conductive material that electrically couples the electrical contact of the circuit substrate to the first buried interconnect of the first semiconductor die.
Example 7: The device or method of any of Examples 1-6 where the circuit substrate is a second semiconductor die. The second semiconductor die includes electronic devices integrally formed in a second device region that forms part of a volume of semiconductor material disposed between the upper surface and the lower surface of the second semiconductor die; and a second electrically-conductive buried interconnect formed within the second volume of semiconductor material between the second device region and the lower surface of the second semiconductor die and extending from an interior portion of the second semiconductor die toward a first edge of the second semiconductor die along a lateral direction that is parallel to the upper and lower surfaces of the second semiconductor die. The second buried interconnect is coupled to the electrical contact that is exposed at the first edge of the circuit substrate.
Example 8: The device or method of any one of Examples 1-7 where the semiconductor die is disposed on a carrier substrate and including an electrically conductive extended lead facing the first edge of the first semiconductor die and extending vertically from the carrier substrate. The first semiconductor die is coupled to the extended lead at a first location along the extended lead via a volume of electrically conductive material that is coupled to the first buried interconnect at the first edge of the first semiconductor die. An additional die is electrically coupled to the extended lead at a second location along the extended lead that is disposed above the first location.
Example 9: The device or method of any one of Examples 1-8 where the semiconductor die is disposed on a carrier substrate and the first buried interconnect includes one or more vertical shafts lined with metal which extend toward the lower surface of the first semiconductor die that are exposed at the bottom surface of the first semiconductor die. The semiconductor die is metallurgically bonded to the carrier substrate via material of the one or more vertical shafts that is exposed at the bottom surface of the first semiconductor die.
Example 10: The device or method of any one of Examples 1-9 where the first buried interconnect is coupled to a supply voltage node or a reference voltage node. The first buried interconnect forms part of an electrically-conductive supply voltage manifold configured to distribute electrical power from the supply voltage node to multiple electronic devices within the first device region.
Example 11: The device or method of any of Examples 1-10 where the first buried interconnect extends from the interior portion of the first semiconductor die to the first edge of the first semiconductor die along the lateral direction that is parallel to the upper and lower surfaces of the first semiconductor die. The first buried interconnect is exposed at the first edge of the first semiconductor die.
Example 12: A device or method that includes a first semiconductor die having an upper surface, a lower surface, and a first volume of semiconductor material disposed between the upper surface and the lower surface; electronic devices integrally formed in a first device region that forms part of the first volume of semiconductor material. A first electrically-conductive buried interconnect is formed within the first volume of semiconductor material between the first device region and the lower surface of the first semiconductor die and the first buried interconnect extending along a lateral direction that is parallel to the upper and lower surfaces of the first semiconductor die.
Example 13: The device or method of Example 12, where the first buried interconnect is coupled to a voltage distribution node and where the first buried interconnect forms part of an electrically-conductive voltage distribution manifold configured to distribute electrical power or an electrical signal from the voltage distribution node to multiple electronic devices within the first device region or to couple the multiple electronic devices within the first device region to the voltage distribution node.
Example 14: The device or method of Example 12 or Example 13, where the voltage distribution manifold includes an electrically-conductive first vertical interconnect that extends vertically through the first device region of the first volume of semiconductor material and is electrically coupled to the first buried interconnect within the first volume of semiconductor material.
Example 15: The device or method of any one of Examples 12-14, where the first vertical interconnect couples the first buried interconnect to the voltage distribution node.
Example 16: The device or method of any one of Examples 12-15, where the first vertical interconnect is coupled to a conductive contact disposed on a surface of the first semiconductor die that is above or below the first buried interconnect that is configured to couple the first vertical interconnect to the voltage distribution node.
Example 17: The device or method of any one of Examples 12-16, where the first vertical interconnect via further extends above the first device region into dielectric material disposed above the first device region and the voltage distribution manifold includes the first vertical interconnect and additional electrical interconnections within the dielectric material.
Example 18: The device or method of any one of Examples 12-17, where the voltage distribution node is a supply voltage node or a reference potential node.
Example 19: The device or method of any of Examples 12-18 where the first buried interconnect is electrically coupled to one or more of the electronic devices of the first device region.
The preceding detailed description and examples are merely illustrative in nature and are not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.
It should be understood that this invention is not limited in its application to the details of construction and the arrangement of components set forth in the preceding description or illustrated in the accompanying drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. Also, it is to be understood that the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Unless specified or limited otherwise, the terms “mounted,” “connected,” “supported,” and “coupled” and variations thereof are used broadly and encompass both direct and indirect mountings, connections, supports, and couplings. Further, “connected” and “coupled” are not restricted to physical or mechanical connections or couplings.
The preceding discussion is presented to enable a person skilled in the art to make and use embodiments of the invention. Various modifications to the illustrated embodiments will be readily apparent to those skilled in the art, and the generic principles herein can be applied to other embodiments and applications without departing from embodiments of the invention. Thus, embodiments of the invention are not intended to be limited to embodiments shown, but are to be accorded the widest scope consistent with the principles and features disclosed herein. The preceding detailed description is to be read with reference to the figures, in which like elements in different figures have like reference numerals. The Figures, which are not necessarily to scale, depict selected embodiments and are not intended to limit the scope of embodiments of the invention. Skilled artisans will recognize the examples provided herein have many useful alternatives and fall within the scope of embodiments of the invention.
The connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in one or more embodiments of the subject matter. In addition, certain terminology may also be used herein for the purpose of reference only, and thus are not intended to be limiting, and the terms “first,” “second” and other such numerical terms referring to structures do not imply a sequence or order unless clearly indicated by the context.
The foregoing description refers to elements or nodes or features being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element is directly or indirectly joined to (or directly or indirectly communicates with, electrically or otherwise) another element, and not necessarily mechanically. Thus, although the schematic shown in the figures depict one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in one or more embodiments of the depicted subject matter.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202341087415 | Dec 2023 | IN | national |
