F. Erich Goetting

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods of implementing and modeling interconnect lines at optional...
- Patent number 8,001,511
- Issue date Aug 16, 2011
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic reconfiguration of a system monitor (DRPORT)
- Patent number 7,599,299
- Issue date Oct 6, 2009
- Xilinx, Inc.
- F. Erich Goetting
- G01 - MEASURING TESTING
Information Patent Grant
Methods of providing a family of related integrated circuits of dif...
- Patent number 7,498,192
- Issue date Mar 3, 2009
- Xilinx, Inc.
- F. Erich Goetting
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for providing frequency synthesis and phase al...
- Patent number 7,499,513
- Issue date Mar 3, 2009
- Xilinx, Inc.
- David E. Tetzlaff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Yield-enhancing methods of providing a family of scaled integrated...
- Patent number 7,491,576
- Issue date Feb 17, 2009
- Xilinx, Inc.
- Steven P. Young
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of implementing and modeling interconnect lines at optional...
- Patent number 7,451,421
- Issue date Nov 11, 2008
- Xilinx, Inc.
- Trevor J. Bauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of providing families of integrated circuits with similar d...
- Patent number 7,402,443
- Issue date Jul 22, 2008
- Xilinx, Inc.
- Raymond C. Pang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-product die configurable as two or more programmable integrat...
- Patent number 7,345,507
- Issue date Mar 18, 2008
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System monitor in a programmable logic device
- Patent number 7,235,999
- Issue date Jun 26, 2007
- Xilinx, Inc.
- F. Erich Goetting
- G01 - MEASURING TESTING
Information Patent Grant
Reconfiguration port for dynamic reconfiguration-system monitor int...
- Patent number 7,233,532
- Issue date Jun 19, 2007
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System monitor in a programmable logic device
- Patent number 7,230,445
- Issue date Jun 12, 2007
- Xilinx, Inc.
- F. Erich Goetting
- G01 - MEASURING TESTING
Information Patent Grant
Reconfiguration port for dynamic reconfiguration
- Patent number 7,218,137
- Issue date May 15, 2007
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronized multi-output digital clock manager
- Patent number 7,187,742
- Issue date Mar 6, 2007
- Xilinx, Inc.
- John D. Logue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System monitor in a programmable logic device
- Patent number 7,138,820
- Issue date Nov 21, 2006
- Xilinx, Inc.
- F. Erich Goetting
- G01 - MEASURING TESTING
Information Patent Grant
Reconfiguration port for dynamic reconfiguration—sub-frame access f...
- Patent number 7,126,372
- Issue date Oct 24, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reconfiguration port for dynamic reconfiguration-controller
- Patent number 7,109,750
- Issue date Sep 19, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital spread spectrum circuitry
- Patent number 7,010,014
- Issue date Mar 7, 2006
- Xilinx, Inc.
- Andrew K. Percey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital phase shifter
- Patent number 6,775,342
- Issue date Aug 10, 2004
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay lock loop with clock phase shifter
- Patent number 6,587,534
- Issue date Jul 1, 2003
- Xilinx, Inc.
- Joseph H. Hassoun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device capable of preserving state data during p...
- Patent number 6,525,562
- Issue date Feb 25, 2003
- Xilinx, Inc.
- David P. Schultz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device capable of preserving user data during pa...
- Patent number 6,507,211
- Issue date Jan 14, 2003
- Xilinx, Inc.
- David P. Schultz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA with a plurality of input reference voltage levels
- Patent number 6,448,809
- Issue date Sep 10, 2002
- Xilinx, Inc.
- F. Erich Goetting
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital clock multiplier and divider with output waveform shaping
- Patent number 6,445,232
- Issue date Sep 3, 2002
- Xilinx, Inc.
- John D. Logue
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with partial battery backup
- Patent number 6,441,641
- Issue date Aug 27, 2002
- Xilinx, Inc.
- Raymond C. Pang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration bus interface circuit for FPGAs
- Patent number 6,429,682
- Issue date Aug 6, 2002
- Xilinx, Inc.
- David P. Schultz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Nonvolatile/battery-backed key in PLD
- Patent number 6,366,117
- Issue date Apr 2, 2002
- Xilinx, Inc.
- Raymond C. Pang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA with a plurality of input reference voltage levels
- Patent number 6,294,930
- Issue date Sep 25, 2001
- Xilinx, Inc.
- F. Erich Goetting
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay lock loop with clock phase shifter
- Patent number 6,289,068
- Issue date Sep 11, 2001
- Xilinx, Inc.
- Joseph H. Hassoun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration bus interface circuit for FPGAS
- Patent number 6,262,596
- Issue date Jul 17, 2001
- Xilinx, Inc.
- David P. Schultz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and structure for configuring FPGAS
- Patent number 6,204,687
- Issue date Mar 20, 2001
- Xilinx, Inc.
- David P. Schultz
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM MONITOR IN A PROGRAMMABLE LOGIC DEVICE
- Publication number 20070115024
- Publication date May 24, 2007
- Xilinx, Inc.
- F. Erich Goetting
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System monitor in a programmable logic device
- Publication number 20070040717
- Publication date Feb 22, 2007
- Xilinx, Inc.
- F. Erich Goetting
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dynamic reconfiguration of a system monitor (DRPORT)
- Publication number 20050262492
- Publication date Nov 24, 2005
- Xilinx, Inc.
- F. Erich Goetting
- G01 - MEASURING TESTING
Information Patent Application
Reconfiguration port for dynamic reconfiguration
- Publication number 20050248364
- Publication date Nov 10, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Reconfiguration port for dynamic reconfiguration - sub-frame access...
- Publication number 20050242834
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Reconfiguration port for dynamic reconfiguration-system monitor int...
- Publication number 20050246520
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Reconfiguration port for dynamic reconfiguration-controller
- Publication number 20050242835
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System monitor in a programmable logic device
- Publication number 20050242836
- Publication date Nov 3, 2005
- Xilinx, Inc.
- F. Erich Goetting
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FPGA with a plurality of input reference voltage levels
- Publication number 20020005735
- Publication date Jan 17, 2002
- Xilinx, Inc.
- F. Erich Goetting
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay lock loop with clock phase shifter
- Publication number 20010033630
- Publication date Oct 25, 2001
- Xilinx, Inc.
- Joseph H. Hassoun
- G06 - COMPUTING CALCULATING COUNTING

F. Erich Goetting

Person

Patents Grantslast 30 patents

Methods of implementing and modeling interconnect lines at optional...

Dynamic reconfiguration of a system monitor (DRPORT)

Methods of providing a family of related integrated circuits of dif...

Method and apparatus for providing frequency synthesis and phase al...

Yield-enhancing methods of providing a family of scaled integrated...

Methods of implementing and modeling interconnect lines at optional...

Methods of providing families of integrated circuits with similar d...

Multi-product die configurable as two or more programmable integrat...

System monitor in a programmable logic device

Reconfiguration port for dynamic reconfiguration-system monitor int...

System monitor in a programmable logic device

Reconfiguration port for dynamic reconfiguration

Synchronized multi-output digital clock manager

System monitor in a programmable logic device

Reconfiguration port for dynamic reconfiguration—sub-frame access f...

Reconfiguration port for dynamic reconfiguration-controller

Digital spread spectrum circuitry

Digital phase shifter

Delay lock loop with clock phase shifter

Programmable logic device capable of preserving state data during p...

Programmable logic device capable of preserving user data during pa...

FPGA with a plurality of input reference voltage levels

Digital clock multiplier and divider with output waveform shaping

Programmable logic device with partial battery backup

Configuration bus interface circuit for FPGAs

Nonvolatile/battery-backed key in PLD

FPGA with a plurality of input reference voltage levels

Delay lock loop with clock phase shifter

Configuration bus interface circuit for FPGAS

Method and structure for configuring FPGAS

Patents Applicationslast 30 patents

SYSTEM MONITOR IN A PROGRAMMABLE LOGIC DEVICE

System monitor in a programmable logic device

Dynamic reconfiguration of a system monitor (DRPORT)

Reconfiguration port for dynamic reconfiguration

Reconfiguration port for dynamic reconfiguration - sub-frame access...

Reconfiguration port for dynamic reconfiguration-system monitor int...

Reconfiguration port for dynamic reconfiguration-controller

System monitor in a programmable logic device

FPGA with a plurality of input reference voltage levels

Delay lock loop with clock phase shifter