Frank R. Keyser III

Person

Colchester, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Receiver deserializer latency trim
- Patent number 9,473,172
- Issue date Oct 18, 2016
- GLOBALFOUNDRIES, INC.
- Leonard R. Chieco
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transmitter serializer latency trim
- Patent number 9,374,098
- Issue date Jun 21, 2016
- GLOBALFOUNDRIES, INC.
- Leonard R. Chieco
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Off-line gain calibration in a time-interleaved analog-to-digital c...
- Patent number 8,587,464
- Issue date Nov 19, 2013
- International Business Machines Corporation
- Anthony R. Bonaccio
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Comparator offset cancellation in a successive approximation analog...
- Patent number 8,493,250
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Anthony R. Bonaccio
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for Viterbi detection of generalized partial r...
- Patent number 6,373,906
- Issue date Apr 16, 2002
- International Business Machines Corporation
- Roy Daron Cideciyan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Field programmable memory array
- Patent number 6,233,191
- Issue date May 15, 2001
- International Business Machines Corporation
- Scott Whitney Gould
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable address decoder for field programmable memory array
- Patent number 6,130,854
- Issue date Oct 10, 2000
- International Business Machines Corporation
- Scott Whitney Gould
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of operating a field programmable memory array with a field...
- Patent number 6,118,707
- Issue date Sep 12, 2000
- International Business Machines Corporation
- Scott Whitney Gould
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field programmable memory array
- Patent number 6,075,745
- Issue date Jun 13, 2000
- International Business Machines Corporation
- Scott Whitney Gould
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable bit line drive modes for memory arrays
- Patent number 6,044,031
- Issue date Mar 28, 2000
- International Business Machines Corporation
- Joseph Andrew Iadanza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cells for field programmable memory array
- Patent number 6,038,192
- Issue date Mar 14, 2000
- International Business Machines Corporation
- Kim P. N. Clinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective connectivity between memory sub-arrays and a hierarchical...
- Patent number 6,023,421
- Issue date Feb 8, 2000
- International Business Machines Corporation
- Kim P. N. Clinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testable programmable gate array and associated LSSD/deterministic...
- Patent number 6,021,513
- Issue date Feb 1, 2000
- International Business Machines Corporation
- Wayne Kevin Beebe
- G01 - MEASURING TESTING
Information Patent Grant
Field programmable memory array
- Patent number 5,949,719
- Issue date Sep 7, 1999
- International Business Machines Corporation
- Kim P. N. Clinton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for implementing write, initialization, and reset in a memor...
- Patent number 5,802,003
- Issue date Sep 1, 1998
- International Business Machines Corporation
- Joseph Andrew Iadanza
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable inverter circuit used in a programmable logic cell
- Patent number 5,781,032
- Issue date Jul 14, 1998
- International Business Machines Corporation
- Allan Robert Bertolet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic cell
- Patent number 5,748,009
- Issue date May 5, 1998
- International Business Machines Corporation
- Allan Robert Bertolet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for programming a gate array using a compressed c...
- Patent number 5,745,734
- Issue date Apr 28, 1998
- International Business Machines Corporation
- David John Craft
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for layout and schematic generation for heterogen...
- Patent number 5,734,582
- Issue date Mar 31, 1998
- International Business Machines Corporation
- Allan Robert Bertolet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable array interconnect latch
- Patent number 5,732,246
- Issue date Mar 24, 1998
- International Business Machines Corporation
- Scott Whitney Gould
- G01 - MEASURING TESTING
Information Patent Grant
Low skew multiplexer network and programmable array clock/reset app...
- Patent number 5,717,346
- Issue date Feb 10, 1998
- International Business Machines Corporation
- Scott Whitney Gould
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable array clock/reset resource
- Patent number 5,703,498
- Issue date Dec 30, 1997
- International Business Machines Corporation
- Scott Whitney Gould
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory mapping method and apparatus to fold sparsely populated stru...
- Patent number 5,692,147
- Issue date Nov 25, 1997
- International Business Machines Corporation
- Wendell Ray Larsen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable array clock/reset resource
- Patent number 5,652,529
- Issue date Jul 29, 1997
- International Business Machines Corporation
- Scott Whitney Gould
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic cell having configurable gates and multiplexers
- Patent number 5,646,546
- Issue date Jul 8, 1997
- International Business Machines Corporation
- Allan Robert Bertolet
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable array interconnect network
- Patent number 5,631,578
- Issue date May 20, 1997
- International Business Machines Corporation
- Kim P. N. Clinton
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
TRANSMITTER SERIALIZER LATENCY TRIM
- Publication number 20150222376
- Publication date Aug 6, 2015
- International Business Machines Corporation
- LEONARD R. CHIECO
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RECEIVER DESERIALIZER LATENCY TRIM
- Publication number 20150222377
- Publication date Aug 6, 2015
- International Business Machines Corporation
- LEONARD R. CHIECO
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
OFF-LINE GAIN CALIBRATION IN A TIME-INTERLEAVED ANALOG-TO-DIGITAL C...
- Publication number 20130176154
- Publication date Jul 11, 2013
- International Business Machines Corporation
- Anthony R. BONACCIO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
COMPARATOR OFFSET CANCELLATION IN A SUCCESSIVE APPROXIMATION ANALOG...
- Publication number 20130057417
- Publication date Mar 7, 2013
- International Business Machines Corporation
- Anthony R. BONACCIO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT HAVING REGISTER CONFIGURATION SETS
- Publication number 20040143715
- Publication date Jul 22, 2004
- International Business Machines Corporation
- Anthony R. Bonaccio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Read channel with automatic servo track writer
- Publication number 20040090695
- Publication date May 13, 2004
- International Business Machines Corporation
- Valerie Chickanosky
- G11 - INFORMATION STORAGE

Frank R. Keyser III

Person

Patents Grantslast 30 patents

Receiver deserializer latency trim

Transmitter serializer latency trim

Off-line gain calibration in a time-interleaved analog-to-digital c...

Comparator offset cancellation in a successive approximation analog...

Method and apparatus for Viterbi detection of generalized partial r...

Field programmable memory array

Programmable address decoder for field programmable memory array

Method of operating a field programmable memory array with a field...

Field programmable memory array

Programmable bit line drive modes for memory arrays

Memory cells for field programmable memory array

Selective connectivity between memory sub-arrays and a hierarchical...

Testable programmable gate array and associated LSSD/deterministic...

Field programmable memory array

System for implementing write, initialization, and reset in a memor...

Programmable inverter circuit used in a programmable logic cell

Programmable logic cell

Method and system for programming a gate array using a compressed c...

Method and system for layout and schematic generation for heterogen...

Programmable array interconnect latch

Low skew multiplexer network and programmable array clock/reset app...

Programmable array clock/reset resource

Memory mapping method and apparatus to fold sparsely populated stru...

Programmable array clock/reset resource

Programmable logic cell having configurable gates and multiplexers

Programmable array interconnect network

Patents Applicationslast 30 patents

TRANSMITTER SERIALIZER LATENCY TRIM

RECEIVER DESERIALIZER LATENCY TRIM

OFF-LINE GAIN CALIBRATION IN A TIME-INTERLEAVED ANALOG-TO-DIGITAL C...

COMPARATOR OFFSET CANCELLATION IN A SUCCESSIVE APPROXIMATION ANALOG...

INTEGRATED CIRCUIT HAVING REGISTER CONFIGURATION SETS

Read channel with automatic servo track writer