Gayle W. Miller

Person

Fort Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low leakage FINFETs
- Patent number 8,378,414
- Issue date Feb 19, 2013
- Atmel Corporation
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and materials to control doping profile in integrated circui...
- Patent number 7,629,649
- Issue date Dec 8, 2009
- Atmel Corporation
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polish stop and sealing layer for manufacture of semiconductor devi...
- Patent number 7,435,661
- Issue date Oct 14, 2008
- Atmel Corporation
- Gayle Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DMOS device with sealed channel processing
- Patent number 7,407,851
- Issue date Aug 5, 2008
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit isolation utilizing MeV implantation
- Patent number 6,885,078
- Issue date Apr 26, 2005
- LSI Logic Corporation
- Donald M. Bartlett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for composing a dielectric layer within an interconnect stru...
- Patent number 6,806,162
- Issue date Oct 19, 2004
- LSI Logic Corporation
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for determining temperature of a semiconductor...
- Patent number 6,794,310
- Issue date Sep 21, 2004
- LSI Logic Corporation
- Gayle W. Miller
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method for composing a dielectric layer within an interconnect stru...
- Patent number 6,614,097
- Issue date Sep 2, 2003
- LSI Logic Corporation
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for enhancing anti-reflective coatings used in photolithogra...
- Patent number 6,527,867
- Issue date Mar 4, 2003
- LSI Logic Corporation
- Kunal Taravade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device comprising low dielectric constant materi...
- Patent number 6,522,005
- Issue date Feb 18, 2003
- Hyundai Electronics America Inc
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low dielectric constant material in integrated circuit
- Patent number 6,522,006
- Issue date Feb 18, 2003
- Hyundai Electronics America Inc
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with reduced cross talk
- Patent number 6,504,249
- Issue date Jan 7, 2003
- Hyundai Electronics America Inc
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with reduced cross talk
- Patent number 6,504,250
- Issue date Jan 7, 2003
- Hyundai Electronics America Inc
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for using low dielectric constant material in integrated cir...
- Patent number 6,448,653
- Issue date Sep 10, 2002
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Encapsulated-metal vertical-interdigitated capacitor and damascene...
- Patent number 6,441,419
- Issue date Aug 27, 2002
- LSI Logic Corporation
- Gregory A. Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Endpoint detection method and apparatus which utilize a chelating a...
- Patent number 6,383,332
- Issue date May 7, 2002
- LSI Logic Corporation
- Gail D. Shelton
- B24 - GRINDING POLISHING
Information Patent Grant
Method of electrically connecting and isolating components with ver...
- Patent number 6,358,837
- Issue date Mar 19, 2002
- LSI Logic Corporation
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual gate oxide process for deep submicron ICS
- Patent number 6,358,819
- Issue date Mar 19, 2002
- LSI Logic Corporation
- Gail D. Shelton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for determining temperature of a semiconductor...
- Patent number 6,328,802
- Issue date Dec 11, 2001
- LSI Logic Corporation
- Gayle W. Miller
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Circuit isolation utilizing MeV implantation
- Patent number 6,319,793
- Issue date Nov 20, 2001
- LSI Logic Corporation
- Donald M. Bartlett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for deposition of porous silica dielectrics
- Patent number 6,287,987
- Issue date Sep 11, 2001
- LSI Logic Corporation
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing semiconductor device having a recessed gate...
- Patent number 6,277,707
- Issue date Aug 21, 2001
- LSI Logic Corporation
- Brian R. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for detecting an ion-implanted polishing endpo...
- Patent number 6,268,224
- Issue date Jul 31, 2001
- LSI Logic Corporation
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Endpoint detection method and apparatus which utilize an endpoint p...
- Patent number 6,258,205
- Issue date Jul 10, 2001
- LSI Logic Corporation
- Brynne K. Chisholm
- B24 - GRINDING POLISHING
Information Patent Grant
Method for enhancing anti-reflective coatings used in photolithogra...
- Patent number 6,225,215
- Issue date May 1, 2001
- LSI Logic Corporation
- Kunal Taravade
- G02 - OPTICS
Information Patent Grant
Integrated circuit device with reduced cross talk
- Patent number 6,208,029
- Issue date Mar 27, 2001
- Hyundai Electronics America
- Derryl D. J. Allman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High reliability bearing structure
- Patent number 6,206,573
- Issue date Mar 27, 2001
- LSI Logic Corporation
- Gayle W. Miller
- F16 - ENGINEERING ELEMENTS AND UNITS GENERAL MEASURES FOR PRODUCING AND MAINT...
Information Patent Grant
Copper contamination control of in-line probe instruments
- Patent number 6,150,175
- Issue date Nov 21, 2000
- LSI Logic Corporation
- Gail D. Shelton
- B08 - CLEANING
Information Patent Grant
Method and arrangement for fabricating a semiconductor device
- Patent number 6,136,719
- Issue date Oct 24, 2000
- LSI Logic Corporation
- Gayle W. Miller
- B24 - GRINDING POLISHING
Information Patent Grant
Simple bicmos process for creation of low trigger voltage SCR and z...
- Patent number 6,130,117
- Issue date Oct 10, 2000
- LSI Logic Corporation
- John D. Walker
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method And Manufacturing Low Leakage Mosfets And FinFets
- Publication number 20110260250
- Publication date Oct 27, 2011
- ATMEL CORPORATION
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DMOS DEVICE WITH SEALED CHANNEL PROCESSING
- Publication number 20080290426
- Publication date Nov 27, 2008
- ATMEL CORPORATION
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR MONITORING A PROCESS
- Publication number 20080201088
- Publication date Aug 21, 2008
- ATMEL CORPORATION
- Gayle W. Miller
- G01 - MEASURING TESTING
Information Patent Application
REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION
- Publication number 20080173940
- Publication date Jul 24, 2008
- ATMEL CORPORATION
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and system for creating self-aligned twin wells with co-plan...
- Publication number 20080166862
- Publication date Jul 10, 2008
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION
- Publication number 20080135933
- Publication date Jun 12, 2008
- ATMEL CORPORATION
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH VOLTAGE VERTICALLY ORIENTED EEPROM DEVICE
- Publication number 20080108212
- Publication date May 8, 2008
- ATMEL CORPORATION
- Thomas S. Moss
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND MATERIALS TO CONTROL DOPING PROFILE IN INTEGRATED CIRCUI...
- Publication number 20070264795
- Publication date Nov 15, 2007
- ATMEL CORPORATION
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and manufacturing low leakage MOSFETs and FinFETs
- Publication number 20070228425
- Publication date Oct 4, 2007
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DMOS device with sealed channel processing
- Publication number 20070221965
- Publication date Sep 27, 2007
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a self-aligned twin well region with simplified...
- Publication number 20070212840
- Publication date Sep 13, 2007
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REGISTRATION MARK WITHIN AN OVERLAP OF DOPANT REGIONS
- Publication number 20070207589
- Publication date Sep 6, 2007
- ATMEL CORPORATION
- Franz Dietz
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Locos self-aligned twin well with a co-planar silicon surface
- Publication number 20070178677
- Publication date Aug 2, 2007
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Polish stop and sealing layer for manufacture of semiconductor devi...
- Publication number 20070178660
- Publication date Aug 2, 2007
- Gayle Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrostatic discharge (ESD) protection structure and a circuit us...
- Publication number 20070120190
- Publication date May 31, 2007
- Atmel Corporation
- Stefan Schwantes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Registration mark within an overlap of dopant regions
- Publication number 20070048959
- Publication date Mar 1, 2007
- Franz Dietz
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Reduced electric field DMOS using self-aligned trench isolation
- Publication number 20070018273
- Publication date Jan 25, 2007
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Protective envelope for a chip card
- Publication number 20060124747
- Publication date Jun 15, 2006
- Irwin D. Rathbun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit isolation utilizing MeV implantation
- Publication number 20030092222
- Publication date May 15, 2003
- Donald M. Bartlett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual gate oxide process for deep submicron ICS
- Publication number 20020058382
- Publication date May 16, 2002
- Gail D. Shelton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for deposition of porous silica dielectrics
- Publication number 20010051403
- Publication date Dec 13, 2001
- Gayle W. Miller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having a recessed gate structure and method of...
- Publication number 20010042874
- Publication date Nov 22, 2001
- Brian R. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT ISOLATION UTILIZING MEV IMPLANTATION
- Publication number 20010041418
- Publication date Nov 15, 2001
- DONALD M. BARTLETT
- H01 - BASIC ELECTRIC ELEMENTS

Gayle W. Miller

Person

Patents Grantslast 30 patents

Low leakage FINFETs

Method and materials to control doping profile in integrated circui...

Polish stop and sealing layer for manufacture of semiconductor devi...

DMOS device with sealed channel processing

Circuit isolation utilizing MeV implantation

Method for composing a dielectric layer within an interconnect stru...

Method and apparatus for determining temperature of a semiconductor...

Method for composing a dielectric layer within an interconnect stru...

Method for enhancing anti-reflective coatings used in photolithogra...

Integrated circuit device comprising low dielectric constant materi...

Low dielectric constant material in integrated circuit

Integrated circuit device with reduced cross talk

Integrated circuit device with reduced cross talk

Method for using low dielectric constant material in integrated cir...

Encapsulated-metal vertical-interdigitated capacitor and damascene...

Endpoint detection method and apparatus which utilize a chelating a...

Method of electrically connecting and isolating components with ver...

Dual gate oxide process for deep submicron ICS

Method and apparatus for determining temperature of a semiconductor...

Circuit isolation utilizing MeV implantation

Method and apparatus for deposition of porous silica dielectrics

Method of manufacturing semiconductor device having a recessed gate...

Method and apparatus for detecting an ion-implanted polishing endpo...

Endpoint detection method and apparatus which utilize an endpoint p...

Method for enhancing anti-reflective coatings used in photolithogra...

Integrated circuit device with reduced cross talk

High reliability bearing structure

Copper contamination control of in-line probe instruments

Method and arrangement for fabricating a semiconductor device

Simple bicmos process for creation of low trigger voltage SCR and z...

Patents Applicationslast 30 patents

Method And Manufacturing Low Leakage Mosfets And FinFets

DMOS DEVICE WITH SEALED CHANNEL PROCESSING

SYSTEM AND METHOD FOR MONITORING A PROCESS

REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION

Method and system for creating self-aligned twin wells with co-plan...

REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION

HIGH VOLTAGE VERTICALLY ORIENTED EEPROM DEVICE

METHOD AND MATERIALS TO CONTROL DOPING PROFILE IN INTEGRATED CIRCUI...

Method and manufacturing low leakage MOSFETs and FinFETs

DMOS device with sealed channel processing

Method for forming a self-aligned twin well region with simplified...

REGISTRATION MARK WITHIN AN OVERLAP OF DOPANT REGIONS

Locos self-aligned twin well with a co-planar silicon surface

Polish stop and sealing layer for manufacture of semiconductor devi...

Electrostatic discharge (ESD) protection structure and a circuit us...

Registration mark within an overlap of dopant regions

Reduced electric field DMOS using self-aligned trench isolation

Protective envelope for a chip card

Circuit isolation utilizing MeV implantation

Dual gate oxide process for deep submicron ICS

Method and apparatus for deposition of porous silica dielectrics

Semiconductor device having a recessed gate structure and method of...

CIRCUIT ISOLATION UTILIZING MEV IMPLANTATION