Georg Braun

Person

Munchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Distributed command and address bus architecture for a memory modul...
- Patent number 8,161,219
- Issue date Apr 17, 2012
- Qimonda AG
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus termination system and method
- Patent number 8,041,865
- Issue date Oct 18, 2011
- Qimonda AG
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for providing a signal for transmission via a...
- Patent number 7,936,201
- Issue date May 3, 2011
- Qimonda AG
- Edoardo Prete
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed memory architecture
- Patent number 7,848,153
- Issue date Dec 7, 2010
- Qimonda AG
- Michael Bruennert
- G11 - INFORMATION STORAGE
Information Patent Grant
Command protocol for integrated circuits
- Patent number 7,844,798
- Issue date Nov 30, 2010
- Qimonda AG
- Andreas Gärtner
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory dies for flexible use and method for configuring memory dies
- Patent number 7,796,446
- Issue date Sep 14, 2010
- Qimonda AG
- Hermann Ruckerbauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Horizontal dual in-line memory modules
- Patent number 7,771,206
- Issue date Aug 10, 2010
- Qimonda AG
- Michael Bruennert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Apparatus and method for switching an apparatus to a power saving mode
- Patent number 7,721,130
- Issue date May 18, 2010
- Qimonda AG
- Edoardo Prete
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer component for a memory module, and a memory module and a mem...
- Patent number 7,646,650
- Issue date Jan 12, 2010
- Infineon Technologies AG
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory chip with settable termination resistance circuit
- Patent number 7,532,523
- Issue date May 12, 2009
- Qimonda AG
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory and method for adapting the phase relationship...
- Patent number 7,457,174
- Issue date Nov 25, 2008
- Infineon Technologies AG
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer chip and method for controlling one or more memory arrangements
- Patent number 7,447,805
- Issue date Nov 4, 2008
- Infineon Technologies AG
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated semiconductor memory with determination of a chip temper...
- Patent number 7,440,349
- Issue date Oct 21, 2008
- Qimonda AG
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Grant
Concept for interfacing a first circuit requiring a first supply vo...
- Patent number 7,405,591
- Issue date Jul 29, 2008
- Qimonda AG
- Georg Braun
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor memory array with serial control/address bus
- Patent number 7,397,684
- Issue date Jul 8, 2008
- Infineon Technologies, AG
- Hermann Ruckerbauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory arrangement
- Patent number 7,376,802
- Issue date May 20, 2008
- Infineon Technologies AG
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for determining a reference level and evaluating a signal on...
- Patent number 7,362,622
- Issue date Apr 22, 2008
- Infineon Technologies AG
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Grant
DQS signaling in DDR-III memory systems without preamble
- Patent number 7,342,815
- Issue date Mar 11, 2008
- Infineon Technologies, AG
- Hermann Ruckerbauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module and method for operating a memory module in a data me...
- Patent number 7,275,189
- Issue date Sep 25, 2007
- Infineon Technologies AG
- Hermann Ruckerbauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with a temperature sensor, dynamic memory and memory with a...
- Patent number 7,272,063
- Issue date Sep 18, 2007
- Infineon Technologies AG
- Jens Christoph Egerer
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for allocating memory arrangement addresses
- Patent number 7,149,864
- Issue date Dec 12, 2006
- Infineon Technologies AG
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transmitting data into a memory cell array
- Patent number 7,139,290
- Issue date Nov 21, 2006
- Infineon Technologies AG
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for determining the optimum access strategy
- Patent number 7,127,553
- Issue date Oct 24, 2006
- Infineon Technologies AG
- Alexander Benedix
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for calibrating semiconductor devices using a common calibra...
- Patent number 6,958,613
- Issue date Oct 25, 2005
- Infineon Technologies AG
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit
- Patent number 6,911,732
- Issue date Jun 28, 2005
- Infineon Technologies AG
- Simon Muff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory configuration and method for reading a state from and storin...
- Patent number 6,894,330
- Issue date May 17, 2005
- Infineon Technologies AG
- Harald Bachhofer
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic circuit for a method for storing information, said circu...
- Patent number 6,833,731
- Issue date Dec 21, 2004
- Infineon Technologies AG
- Christl Lauterbach
- G01 - MEASURING TESTING
Information Patent Grant
Data processing system having configurable components
- Patent number 6,820,197
- Issue date Nov 16, 2004
- Infineon Technologies AG
- Alexander Benedix
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic circuit with a driver circuit
- Patent number 6,759,874
- Issue date Jul 6, 2004
- Infineon Technologies AG
- Georg Braun
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuration for data transmission in a semiconductor memory syste...
- Patent number 6,724,685
- Issue date Apr 20, 2004
- Infineon Technologies AG
- Georg Braun
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Distributed Command and Address Bus Architecture
- Publication number 20100082871
- Publication date Apr 1, 2010
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Dies for Flexible Use and Method for Configuring Memory Dies
- Publication number 20100074038
- Publication date Mar 25, 2010
- Hermann Ruckerbauer
- G11 - INFORMATION STORAGE
Information Patent Application
Horizontal Dual In-line Memory Modules
- Publication number 20100062621
- Publication date Mar 11, 2010
- MICHAEL BRUENNERT
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
High Speed Memory Architecture
- Publication number 20100046266
- Publication date Feb 25, 2010
- Michael Bruennert
- G11 - INFORMATION STORAGE
Information Patent Application
Stacked Memory Module
- Publication number 20100032820
- Publication date Feb 11, 2010
- Michael Bruennert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bus Termination System and Method
- Publication number 20100030934
- Publication date Feb 4, 2010
- Michael Bruennert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Command Protocol for Integrated Circuits
- Publication number 20090158010
- Publication date Jun 18, 2009
- QIMONDA AG
- Andreas Gartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for providing a signal for transmission via a...
- Publication number 20080155150
- Publication date Jun 26, 2008
- Edoardo Prete
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCEPT FOR INTERFACING A FIRST CIRCUIT REQUIRING A FIRST SUPPLY VO...
- Publication number 20080143386
- Publication date Jun 19, 2008
- Georg Braun
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and method for switching an apparatus to a power saving mode
- Publication number 20080126816
- Publication date May 29, 2008
- Edoardo Prete
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory buffer and method for buffering data
- Publication number 20080126624
- Publication date May 29, 2008
- Edoardo Prete
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for transmitting signals over a signal line
- Publication number 20080123792
- Publication date May 29, 2008
- Edoardo Prete
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MEMORY WITH A TEMPERATURE SENSOR, DYNAMIC MEMORY AND MEMORY WITH A...
- Publication number 20070223299
- Publication date Sep 27, 2007
- Jens Christoph Egerer
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated semiconductor memory with determination of a chip temper...
- Publication number 20070133329
- Publication date Jun 14, 2007
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory array with serial control/address bus
- Publication number 20070058408
- Publication date Mar 15, 2007
- Hermann Ruckerbauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CHIP AND METHOD FOR OPERATING A MEMORY CHIP
- Publication number 20070035326
- Publication date Feb 15, 2007
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor memory and method for adapting the phase relationship...
- Publication number 20060262613
- Publication date Nov 23, 2006
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Application
Buffer component for a memory module, and a memory module and a mem...
- Publication number 20060227627
- Publication date Oct 12, 2006
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory module and memory configuration with stub-free signal lines...
- Publication number 20060202328
- Publication date Sep 14, 2006
- Infineon Technologies AG
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit
- Publication number 20060092715
- Publication date May 4, 2006
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Application
DQS signaling in DDR-III memory systems without preamble
- Publication number 20060062039
- Publication date Mar 23, 2006
- Hermann Ruckerbauer
- G11 - INFORMATION STORAGE
Information Patent Application
Memory arrangement
- Publication number 20050038966
- Publication date Feb 17, 2005
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Synchronous memory system and also method and protocol for communic...
- Publication number 20040230759
- Publication date Nov 18, 2004
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffer chip and method for actuating one or more memory arrangements
- Publication number 20040228166
- Publication date Nov 18, 2004
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and circuit for allocating memory arrangement addresses
- Publication number 20040225856
- Publication date Nov 11, 2004
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory module and method for operating a memory module in a data me...
- Publication number 20040151038
- Publication date Aug 5, 2004
- Hermann Ruckerbauer
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit
- Publication number 20040145036
- Publication date Jul 29, 2004
- Simon Muff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for determining the optimum access strategy
- Publication number 20040117800
- Publication date Jun 17, 2004
- Alexander Benedix
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory module and memory configuration with stub-free signal lines...
- Publication number 20040085795
- Publication date May 6, 2004
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Application
Method for calibrating semiconductor devices using a common calibra...
- Publication number 20040080322
- Publication date Apr 29, 2004
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING

Georg Braun

Person

Patents Grantslast 30 patents

Distributed command and address bus architecture for a memory modul...

Bus termination system and method

Apparatus and method for providing a signal for transmission via a...

High speed memory architecture

Command protocol for integrated circuits

Memory dies for flexible use and method for configuring memory dies

Horizontal dual in-line memory modules

Apparatus and method for switching an apparatus to a power saving mode

Buffer component for a memory module, and a memory module and a mem...

Memory chip with settable termination resistance circuit

Semiconductor memory and method for adapting the phase relationship...

Buffer chip and method for controlling one or more memory arrangements

Integrated semiconductor memory with determination of a chip temper...

Concept for interfacing a first circuit requiring a first supply vo...

Semiconductor memory array with serial control/address bus

Memory arrangement

System for determining a reference level and evaluating a signal on...

DQS signaling in DDR-III memory systems without preamble

Memory module and method for operating a memory module in a data me...

Memory with a temperature sensor, dynamic memory and memory with a...

Method and circuit for allocating memory arrangement addresses

Transmitting data into a memory cell array

Method for determining the optimum access strategy

Method for calibrating semiconductor devices using a common calibra...

Integrated circuit

Memory configuration and method for reading a state from and storin...

Electronic circuit for a method for storing information, said circu...

Data processing system having configurable components

Electronic circuit with a driver circuit

Configuration for data transmission in a semiconductor memory syste...

Patents Applicationslast 30 patents

Distributed Command and Address Bus Architecture

Memory Dies for Flexible Use and Method for Configuring Memory Dies

Horizontal Dual In-line Memory Modules

High Speed Memory Architecture

Stacked Memory Module

Bus Termination System and Method

Command Protocol for Integrated Circuits

Apparatus and method for providing a signal for transmission via a...

CONCEPT FOR INTERFACING A FIRST CIRCUIT REQUIRING A FIRST SUPPLY VO...

Apparatus and method for switching an apparatus to a power saving mode

Memory buffer and method for buffering data

Apparatus and method for transmitting signals over a signal line

MEMORY WITH A TEMPERATURE SENSOR, DYNAMIC MEMORY AND MEMORY WITH A...

Integrated semiconductor memory with determination of a chip temper...

Semiconductor memory array with serial control/address bus

MEMORY CHIP AND METHOD FOR OPERATING A MEMORY CHIP

Semiconductor memory and method for adapting the phase relationship...

Buffer component for a memory module, and a memory module and a mem...

Memory module and memory configuration with stub-free signal lines...

Circuit

DQS signaling in DDR-III memory systems without preamble

Memory arrangement

Synchronous memory system and also method and protocol for communic...

Buffer chip and method for actuating one or more memory arrangements

Method and circuit for allocating memory arrangement addresses

Memory module and method for operating a memory module in a data me...

Integrated circuit

Method for determining the optimum access strategy

Memory module and memory configuration with stub-free signal lines...

Method for calibrating semiconductor devices using a common calibra...