Henry Lui

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuits with clock selection circuitry
- Patent number 9,515,880
- Issue date Dec 6, 2016
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for aligning and reducing skew in serial data signals
- Patent number 8,994,425
- Issue date Mar 31, 2015
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for low-skew channel bonding
- Patent number 8,812,893
- Issue date Aug 19, 2014
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Heterogeneous high-speed serial interface system with phase-locked...
- Patent number 8,812,755
- Issue date Aug 19, 2014
- Altera Corporation
- Surinder Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Modular digital signal processing circuitry with optionally usable,...
- Patent number 8,751,551
- Issue date Jun 10, 2014
- Altera Corporation
- Keone Streicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for determining clock uncertainties
- Patent number 8,739,099
- Issue date May 27, 2014
- Altera Corporation
- Victor R. Maruri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous high-speed serial interface system with phase-locked...
- Patent number 8,700,825
- Issue date Apr 15, 2014
- Altera Corporation
- Surinder Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplier-accumulator circuitry and methods
- Patent number 8,645,450
- Issue date Feb 4, 2014
- Altera Corporation
- Kok Heng Choe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular digital signal processing circuitry with optionally usable,...
- Patent number 8,620,977
- Issue date Dec 31, 2013
- Altera Corporation
- Keone Streicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for providing clock signals in clock networks
- Patent number 8,581,653
- Issue date Nov 12, 2013
- Altera Corporation
- Victor Maruri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for serial interfaces with shared datapaths
- Patent number 8,571,059
- Issue date Oct 29, 2013
- Altera Corporation
- Arch Zaliznyak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular digital signal processing circuitry with optionally usable,...
- Patent number 8,549,055
- Issue date Oct 1, 2013
- Altera Corporation
- Keone Streicher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DSP block for implementing large multiplier on a programmable integ...
- Patent number 8,307,023
- Issue date Nov 6, 2012
- Altera Corporation
- Wai-Bor Leung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock data recovery circuitry associated with programmable logic de...
- Patent number 7,684,532
- Issue date Mar 23, 2010
- Altera Corporation
- Edward Aung
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable current charge pump with modular switch circuit
- Patent number 7,570,105
- Issue date Aug 4, 2009
- Altera Corporation
- Sun Woo Baek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock data recovery circuitry associated with programmable logic de...
- Patent number 7,333,570
- Issue date Feb 19, 2008
- Altera Corporation
- Edward Aung
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced passgate structures for reducing leakage current
- Patent number 7,292,065
- Issue date Nov 6, 2007
- Altera Corporation
- Henry Y. Lui
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock data recovery circuitry associated with programmable logic de...
- Patent number 7,227,918
- Issue date Jun 5, 2007
- Altera Corporation
- Edward Aung
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital phase locked loop circuitry and methods
- Patent number 7,138,837
- Issue date Nov 21, 2006
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Byte alignment for serial data receiver
- Patent number 7,046,174
- Issue date May 16, 2006
- Altera Corporation
- Henry Y. Lui
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Programmable logic resource with data transfer synchronization
- Patent number 7,003,423
- Issue date Feb 21, 2006
- Altera Corporation
- Malik Kabani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits and techniques for conditioning differential signals
- Patent number 6,985,021
- Issue date Jan 10, 2006
- Altera Corporation
- Arch Zaliznyak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Byte alignment for serial data receiver
- Patent number 6,970,117
- Issue date Nov 29, 2005
- Altera Corporation
- Henry Y. Lui
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Byte alignment for serial data receiver
- Patent number 6,724,328
- Issue date Apr 20, 2004
- Altera Corporation
- Henry Y. Lui
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Variable slew control for output buffers
- Patent number 5,568,081
- Issue date Oct 22, 1996
- Cypress Semiconductor, Corporation
- Henry Y. Lui
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Clock Data Recovery Circuitry Associated With Programmable Logic De...
- Publication number 20170155529
- Publication date Jun 1, 2017
- Altera Corporation
- Edward Aung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HETEROGENEOUS HIGH-SPEED SERIAL INTERFACE SYSTEM ARCHITECTURE
- Publication number 20140176188
- Publication date Jun 26, 2014
- Altera Corporation
- Surinder SINGH
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...
- Publication number 20140082035
- Publication date Mar 20, 2014
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Aligning and Reducing Skew in Serial Data Signals
- Publication number 20140035642
- Publication date Feb 6, 2014
- Altera Corporation
- Ramanand Venkata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...
- Publication number 20130332497
- Publication date Dec 12, 2013
- Altera Corporation
- Keone Streicher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock data recovery circuitry associated with programmable logic de...
- Publication number 20080031385
- Publication date Feb 7, 2008
- Altera Corporation
- Edward Aung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ENHANCED PASSGATE STRUCTURES FOR REDUCING LEAKAGE CURRENT
- Publication number 20060028240
- Publication date Feb 9, 2006
- Altera Corporation
- Henry Y. Lui
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digital phase locked loop circuitry and methods
- Publication number 20040140837
- Publication date Jul 22, 2004
- Altera Corporation
- Ramanand Venkata
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clock data recovery circuitry associated with programmable logic de...
- Publication number 20030212930
- Publication date Nov 13, 2003
- Altera Corporation
- Edward Aung
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clock data recovery circuitry associated with programmable logic de...
- Publication number 20010033188
- Publication date Oct 25, 2001
- Edward Aung
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Integrated circuits with clock selection circuitry

Techniques for aligning and reducing skew in serial data signals

Apparatus and methods for low-skew channel bonding

Heterogeneous high-speed serial interface system with phase-locked...

Modular digital signal processing circuitry with optionally usable,...

Method and apparatus for determining clock uncertainties

Heterogeneous high-speed serial interface system with phase-locked...

Multiplier-accumulator circuitry and methods

Modular digital signal processing circuitry with optionally usable,...

Techniques for providing clock signals in clock networks

Apparatus and methods for serial interfaces with shared datapaths

Modular digital signal processing circuitry with optionally usable,...

DSP block for implementing large multiplier on a programmable integ...

Clock data recovery circuitry associated with programmable logic de...

Variable current charge pump with modular switch circuit

Clock data recovery circuitry associated with programmable logic de...

Enhanced passgate structures for reducing leakage current

Clock data recovery circuitry associated with programmable logic de...

Digital phase locked loop circuitry and methods

Byte alignment for serial data receiver

Programmable logic resource with data transfer synchronization

Circuits and techniques for conditioning differential signals

Byte alignment for serial data receiver

Byte alignment for serial data receiver

Variable slew control for output buffers

Patents Applicationslast 30 patents

Clock Data Recovery Circuitry Associated With Programmable Logic De...

HETEROGENEOUS HIGH-SPEED SERIAL INTERFACE SYSTEM ARCHITECTURE

MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...

Techniques for Aligning and Reducing Skew in Serial Data Signals

MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE,...

Clock data recovery circuitry associated with programmable logic de...

ENHANCED PASSGATE STRUCTURES FOR REDUCING LEAKAGE CURRENT

Digital phase locked loop circuitry and methods

Clock data recovery circuitry associated with programmable logic de...

Clock data recovery circuitry associated with programmable logic de...