Hidehiko Shiraiwa

Person

Gresham, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Non-volatile memory with silicided bit line contacts
- Patent number 11,183,509
- Issue date Nov 23, 2021
- Cypress Semiconductor Corporation
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory with silicided bit line contacts
- Patent number 10,692,877
- Issue date Jun 23, 2020
- Cypress Semiconductor Corporation
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for manufacturing self-aligned STI with single poly
- Patent number 10,622,370
- Issue date Apr 14, 2020
- MONTEREY RESEARCH, LLC
- Tim Thurgate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory with silicided bit line contacts
- Patent number 9,666,591
- Issue date May 30, 2017
- Cypress Semiconductor Corporation
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrating transistors with different poly-silicon heights on the...
- Patent number 9,431,503
- Issue date Aug 30, 2016
- Cypress Semiconductor Corporation
- Chuan Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for manufacturing self-aligned STI with single poly
- Patent number 9,276,007
- Issue date Mar 1, 2016
- Cypress Semiconductor Corporation
- Tim Thurgate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory with silicided bit line contacts
- Patent number 9,252,154
- Issue date Feb 2, 2016
- Cypress Semiconductor Corporation
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leakage reducing writeline charge protection circuit
- Patent number 9,196,624
- Issue date Nov 24, 2015
- Cypress Semiconductor Corporation
- Bradley Marc Davis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow bipolar junction transistor
- Patent number 9,111,985
- Issue date Aug 18, 2015
- Cypress Semiconductor Corporation
- Alok Nandini Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-Volatile memory with silicided bit line contacts
- Patent number 8,866,213
- Issue date Oct 21, 2014
- Spansion LLC
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell system with multiple nitride layers
- Patent number 8,809,936
- Issue date Aug 19, 2014
- GLOBALFOUNDRIES Inc.
- Lei Xue
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory manufacturing process with bitline isolation
- Patent number 8,673,716
- Issue date Mar 18, 2014
- Spansion LLC
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrating transistors with different poly-silicon heights on the...
- Patent number 8,652,907
- Issue date Feb 18, 2014
- Spansion LLC
- Chuan Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned STI with single poly for manufacturing a flash memory...
- Patent number 8,642,441
- Issue date Feb 4, 2014
- Spansion LLC
- Tim Thurgate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and manufacture for embedded flash to achieve high quality s...
- Patent number 8,598,005
- Issue date Dec 3, 2013
- Spansion LLC
- Simon Siu-Sing Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell system with charge trap
- Patent number 8,143,661
- Issue date Mar 27, 2012
- Spansion LLC
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory system with protection layer to cover the memory gate stack...
- Patent number 8,119,477
- Issue date Feb 21, 2012
- Spansion LLC
- Hidehiko Shiraiwa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system with memory system
- Patent number 8,114,736
- Issue date Feb 14, 2012
- GLOBALFOUNDRIES Inc.
- Simon Siu-Sing Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High K stack for non-volatile memory
- Patent number 7,855,114
- Issue date Dec 21, 2010
- Spansion LLC
- Wei Zheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple dual bit memory integrated circuit system
- Patent number 7,692,236
- Issue date Apr 6, 2010
- Spansion LLC
- Michael Brennan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit memory system employing silicon rich layers
- Patent number 7,675,104
- Issue date Mar 9, 2010
- Spansion LLC
- Amol Ramesh Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SONOS memory with inversion bit-lines
- Patent number 7,501,677
- Issue date Mar 10, 2009
- Spansion LLC
- Hidehiko Shiraiwa
- G11 - INFORMATION STORAGE
Information Patent Grant
High K stack for non-volatile memory
- Patent number 7,492,001
- Issue date Feb 17, 2009
- Spansion LLC
- Wei Zheng
- G11 - INFORMATION STORAGE
Information Patent Grant
SONOS memory cell having high-K dielectric
- Patent number 7,446,369
- Issue date Nov 4, 2008
- Spansion, LLC
- Takashi Whitney Orimoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating flash memory devices
- Patent number 7,416,940
- Issue date Aug 26, 2008
- Spansion LLC
- Satoshi Torii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed channel with separated ONO memory device
- Patent number 7,394,125
- Issue date Jul 1, 2008
- FASL LLC
- Jaeyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxygen elimination for device processing
- Patent number 7,381,620
- Issue date Jun 3, 2008
- Spansion LLC
- Boon-Yong Ang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell having enhanced high-K dielectric
- Patent number 7,365,389
- Issue date Apr 29, 2008
- Spansion LLC
- Joong Jeon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for determining wordline critical dimension in a memory arra...
- Patent number 7,339,222
- Issue date Mar 4, 2008
- Spansion LLC
- Meng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method for controlling operation thereof
- Patent number 7,321,511
- Issue date Jan 22, 2008
- Spansion LLC
- Masaru Yano
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Non-Volatile Memory With Silicided Bit Line Contacts
- Publication number 20200411537
- Publication date Dec 31, 2020
- Infineon Technologies LLC
- Ching-Huang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-Volatile Memory With Silicided Bit Line Contacts
- Publication number 20170250192
- Publication date Aug 31, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Ching-Huang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-Volatile Memory With Silicided Bit Line Contacts
- Publication number 20160211271
- Publication date Jul 21, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Ching-Huang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-Volatile Memory With Silicided Bit Line Contacts
- Publication number 20150017795
- Publication date Jan 15, 2015
- SPANSION LLC
- Ching-Huang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR MANUFACTURING SELF-ALIGNED STI WITH SINGLE POLY
- Publication number 20140312409
- Publication date Oct 23, 2014
- SPANSION LLC
- Tim Thurgate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-Volatile Memory With Silicided Bit Line Contacts
- Publication number 20140209993
- Publication date Jul 31, 2014
- SPANSION LLC
- Ching-Huang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE...
- Publication number 20140117435
- Publication date May 1, 2014
- SPANSION LLC
- Chuan LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Leakage Reducing Writeline Charge Protection Circuit
- Publication number 20140015138
- Publication date Jan 16, 2014
- SPANSION LLC
- Bradley Marc DAVIS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND MANUFACTURE FOR EMBEDDED FLASH TO ACHIEVE HIGH QUALITY S...
- Publication number 20130023101
- Publication date Jan 24, 2013
- SPANSION LLC
- Simon Siu-Sing Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE...
- Publication number 20120241871
- Publication date Sep 27, 2012
- SPANSION LLC
- Chuan Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH K STACK FOR NON-VOLATILE MEMORY
- Publication number 20090155992
- Publication date Jun 18, 2009
- SPANSION LLC
- Wei ZHENG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM WITH SELECT GATE ERASE
- Publication number 20080150000
- Publication date Jun 26, 2008
- SPANSION LLC
- YouSeok Suh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM
- Publication number 20080150042
- Publication date Jun 26, 2008
- SPANSION LLC
- Simon Siu-Sing Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM
- Publication number 20080150011
- Publication date Jun 26, 2008
- SPANSION LLC
- Simon Siu-Sing Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH IMPLANT OXIDE
- Publication number 20080142874
- Publication date Jun 19, 2008
- SPANSION LLC
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY SYSTEM WITH PROTECTION LAYER TO COVER THE MEMORY GATE STACK...
- Publication number 20080121981
- Publication date May 29, 2008
- SPANSION LLC
- Hidehiko Shiraiwa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A MEMORY DEVICE
- Publication number 20080096357
- Publication date Apr 24, 2008
- Spansion LLC
- Youseok Suh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL SYSTEM WITH CHARGE TRAP
- Publication number 20080083946
- Publication date Apr 10, 2008
- SPANSION LLC
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT MEMORY SYSTEM EMPLOYING SILICON RICH LAYERS
- Publication number 20080023751
- Publication date Jan 31, 2008
- SPANSION LLC
- Amol Ramesh Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL SYSTEM WITH MULTIPLE NITRIDE LAYERS
- Publication number 20080023750
- Publication date Jan 31, 2008
- SPANSION LLC
- Lei Xue
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SONOS memory with inversion bit-lines
- Publication number 20070058442
- Publication date Mar 15, 2007
- Hidehiko Shiraiwa
- G11 - INFORMATION STORAGE
Information Patent Application
SONOS memory cell having high-K dielectric
- Publication number 20070029601
- Publication date Feb 8, 2007
- Takashi Whitney Orimoto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device and method for controlling operation thereof
- Publication number 20060256617
- Publication date Nov 16, 2006
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Application
Self-aligned STI SONOS
- Publication number 20060240635
- Publication date Oct 26, 2006
- Spansion LLC
- Hidehiko Shiraiwa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High K stack for non-volatile memory
- Publication number 20060216888
- Publication date Sep 28, 2006
- Wei Zheng
- G11 - INFORMATION STORAGE
Information Patent Application
CHARGE-TRAPPING MEMORY ARRAYS RESISTANT TO DAMAGE FROM CONTACT HOLE...
- Publication number 20040173918
- Publication date Sep 9, 2004
- Tazrien Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory device having high work function gate and method of erasing...
- Publication number 20040136240
- Publication date Jul 15, 2004
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS
- Publication number 20040014290
- Publication date Jan 22, 2004
- Jean Y. Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory manufacturing process with bitline isolation
- Publication number 20030190786
- Publication date Oct 9, 2003
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Simultaneous formation of charge storage and bitline to wordline is...
- Publication number 20020192910
- Publication date Dec 19, 2002
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS

Hidehiko Shiraiwa

Person

Patents Grantslast 30 patents

Non-volatile memory with silicided bit line contacts

Non-volatile memory with silicided bit line contacts

System and method for manufacturing self-aligned STI with single poly

Non-volatile memory with silicided bit line contacts

Integrating transistors with different poly-silicon heights on the...

System and method for manufacturing self-aligned STI with single poly

Non-volatile memory with silicided bit line contacts

Leakage reducing writeline charge protection circuit

Shallow bipolar junction transistor

Non-Volatile memory with silicided bit line contacts

Memory cell system with multiple nitride layers

Memory manufacturing process with bitline isolation

Integrating transistors with different poly-silicon heights on the...

Self-aligned STI with single poly for manufacturing a flash memory...

Method and manufacture for embedded flash to achieve high quality s...

Memory cell system with charge trap

Memory system with protection layer to cover the memory gate stack...

Integrated circuit system with memory system

High K stack for non-volatile memory

Multiple dual bit memory integrated circuit system

Integrated circuit memory system employing silicon rich layers

SONOS memory with inversion bit-lines

High K stack for non-volatile memory

SONOS memory cell having high-K dielectric

Methods for fabricating flash memory devices

Recessed channel with separated ONO memory device

Oxygen elimination for device processing

Memory cell having enhanced high-K dielectric

Method for determining wordline critical dimension in a memory arra...

Semiconductor device and method for controlling operation thereof

Patents Applicationslast 30 patents

Non-Volatile Memory With Silicided Bit Line Contacts

Non-Volatile Memory With Silicided Bit Line Contacts

Non-Volatile Memory With Silicided Bit Line Contacts

Non-Volatile Memory With Silicided Bit Line Contacts

SYSTEM AND METHOD FOR MANUFACTURING SELF-ALIGNED STI WITH SINGLE POLY

Non-Volatile Memory With Silicided Bit Line Contacts

INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE...

Leakage Reducing Writeline Charge Protection Circuit

METHOD AND MANUFACTURE FOR EMBEDDED FLASH TO ACHIEVE HIGH QUALITY S...

INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE...

HIGH K STACK FOR NON-VOLATILE MEMORY

MEMORY SYSTEM WITH SELECT GATE ERASE

INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM

INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM

INTEGRATED CIRCUIT SYSTEM WITH IMPLANT OXIDE

MEMORY SYSTEM WITH PROTECTION LAYER TO COVER THE MEMORY GATE STACK...

METHOD FOR MANUFACTURING A MEMORY DEVICE

MEMORY CELL SYSTEM WITH CHARGE TRAP

INTEGRATED CIRCUIT MEMORY SYSTEM EMPLOYING SILICON RICH LAYERS

MEMORY CELL SYSTEM WITH MULTIPLE NITRIDE LAYERS

SONOS memory with inversion bit-lines

SONOS memory cell having high-K dielectric

Semiconductor device and method for controlling operation thereof

Self-aligned STI SONOS

High K stack for non-volatile memory

CHARGE-TRAPPING MEMORY ARRAYS RESISTANT TO DAMAGE FROM CONTACT HOLE...

Memory device having high work function gate and method of erasing...

HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS

Memory manufacturing process with bitline isolation

Simultaneous formation of charge storage and bitline to wordline is...