Hirohisa MACHIDA

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Standard cell and semiconductor device
- Patent number 7,956,661
- Issue date Jun 7, 2011
- Renesas Electronics Corporation
- Hirohisa Machida
- G01 - MEASURING TESTING
Information Patent Grant
Viterbi decoder and synchronism controlling method
- Patent number 6,637,003
- Issue date Oct 21, 2003
- Mitsubishi Denki Kabushiki Kaisha
- Michiru Hori
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive equalizer and designing method thereof
- Patent number 6,587,504
- Issue date Jul 1, 2003
- Mitsubishi Denki Kabushiki Kaisha
- Shuji Murakami
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Resampling method and resampler circuit
- Patent number 6,442,580
- Issue date Aug 27, 2002
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor using implicit register addressing
- Patent number 5,875,323
- Issue date Feb 23, 1999
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for generating an object code for a pipeline computer proces...
- Patent number 5,812,845
- Issue date Sep 22, 1998
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Associative memory circuit and TLB circuit
- Patent number 5,805,490
- Issue date Sep 8, 1998
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor circuit for heapsorting
- Patent number 5,603,023
- Issue date Feb 11, 1997
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data sorting apparatus capable of detecting completion of data sort...
- Patent number 5,511,189
- Issue date Apr 23, 1996
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cells interconnection structure including a modified stand...
- Patent number 5,468,977
- Issue date Nov 21, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Associative memory system for performing hit judgment on cache data
- Patent number 5,457,788
- Issue date Oct 10, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware implemented multiplier for performing multiplication of tw...
- Patent number 5,426,599
- Issue date Jun 20, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address translator having a high speed data comparator
- Patent number 5,386,528
- Issue date Jan 31, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Hideki Ando
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Content addressable memory cell and content addressable memory circ...
- Patent number 5,339,268
- Issue date Aug 16, 1994
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device storing two types of binary number data...
- Patent number 5,323,347
- Issue date Jun 21, 1994
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register window system for reducing the need for overflow-write by...
- Patent number 5,233,691
- Issue date Aug 3, 1993
- Mitsubishi Denki Kabushiki Kaisha
- Hideki Ando
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Improved data comparator for comparing plural-bit data at higher speed
- Patent number 5,130,692
- Issue date Jul 14, 1992
- Mitsubishi Denki Kabushiki Kaisha
- Hideaki Ando
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communication control processor
- Patent number 5,048,010
- Issue date Sep 10, 1991
- Mitsubishi Denki Kabushiki Kaisha
- Takeo Nakabayashi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Terminal equipment identifier control circuit
- Patent number 4,963,862
- Issue date Oct 16, 1990
- Mitsubishi Denki Kabushiki Kaisha
- Takeo Nakabayashi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital signal decoding method and circuit therefor
- Patent number 4,943,965
- Issue date Jul 24, 1990
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Periodic signal generator circuit
- Patent number 4,827,157
- Issue date May 2, 1989
- Mitsubishi Denki Kabushiki Kaisha
- Hirohisa Machida
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Arithmetic and logic unit with prior state dependent logic operations
- Patent number 4,821,225
- Issue date Apr 11, 1989
- Mitsubishi Denki Kabushiki Kaisha
- Hideki Ando
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital signal processor with addressable and shifting memory
- Patent number 4,811,267
- Issue date Mar 7, 1989
- Mitsubishi Denki Kabushiki Kaisha
- Hideki Ando
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
STANDARD CELL AND SEMICONDUCTOR DEVICE
- Publication number 20090189663
- Publication date Jul 30, 2009
- RENESAS TECHNOLOGY CORP.
- Hirohisa MACHIDA
- H03 - BASIC ELECTRONIC CIRCUITRY

Hirohisa MACHIDA

Person

Patents Grantslast 30 patents

Standard cell and semiconductor device

Viterbi decoder and synchronism controlling method

Adaptive equalizer and designing method thereof

Resampling method and resampler circuit

Processor using implicit register addressing

Method for generating an object code for a pipeline computer proces...

Associative memory circuit and TLB circuit

Processor circuit for heapsorting

Data sorting apparatus capable of detecting completion of data sort...

Standard cells interconnection structure including a modified stand...

Associative memory system for performing hit judgment on cache data

Hardware implemented multiplier for performing multiplication of tw...

Address translator having a high speed data comparator

Content addressable memory cell and content addressable memory circ...

Semiconductor memory device storing two types of binary number data...

Register window system for reducing the need for overflow-write by...

Improved data comparator for comparing plural-bit data at higher speed

Communication control processor

Terminal equipment identifier control circuit

Digital signal decoding method and circuit therefor

Periodic signal generator circuit

Arithmetic and logic unit with prior state dependent logic operations

Digital signal processor with addressable and shifting memory

Patents Applicationslast 30 patents

STANDARD CELL AND SEMICONDUCTOR DEVICE