Hiroki Tanaka

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Subtractive etch resolution implementing a functional thin metal re...
- Patent number 11,948,848
- Issue date Apr 2, 2024
- Intel Corporation
- Jeremy Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface finishes with low RBTV for fine and mixed bump pitch archit...
- Patent number 11,935,857
- Issue date Mar 19, 2024
- Intel Corporation
- Kristof Darmawaikarta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lithographic cavity formation to enable EMIB bump pitch scaling
- Patent number 11,929,330
- Issue date Mar 12, 2024
- Intel Corporation
- Kristof Darmawikarta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sacrificial dielectric for lithographic via formation to enable via...
- Patent number 11,908,821
- Issue date Feb 20, 2024
- Intel Corporation
- Kristof Darmawikarta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patch accommodating embedded dies having different thicknesses
- Patent number 11,862,619
- Issue date Jan 2, 2024
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitors with nanoislands on conductive plates
- Patent number 11,855,125
- Issue date Dec 26, 2023
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via structures having tapered profiles for embedded interconnect br...
- Patent number 11,721,631
- Issue date Aug 8, 2023
- Intel Corporation
- Jeremy D. Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electromigration resistant and profile consistent contact arrays
- Patent number 11,699,648
- Issue date Jul 11, 2023
- Tahoe Research, LTD.
- Srinivas V. Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via-trace structures
- Patent number 11,652,036
- Issue date May 16, 2023
- Santa Clara
- Jeremy Ecton
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Package architecture utilizing photoimageable dielectric (PID) for...
- Patent number 11,574,874
- Issue date Feb 7, 2023
- Intel Corporation
- Robert A. May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface finishes with low rBTV for fine and mixed bump pitch archit...
- Patent number 11,488,918
- Issue date Nov 1, 2022
- Intel Corporation
- Kristof Darmawaikarta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via structures having tapered profiles for embedded interconnect br...
- Patent number 11,373,951
- Issue date Jun 28, 2022
- Intel Corporation
- Jeremy D. Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lithographic cavity formation to enable EMIB bump pitch scaling
- Patent number 11,322,444
- Issue date May 3, 2022
- Intel Corporation
- Kristof Darmawikarta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electromigration resistant and profile consistent contact arrays
- Patent number 11,309,239
- Issue date Apr 19, 2022
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sacrificial dielectric for lithographic via formation to enable via...
- Patent number 11,264,346
- Issue date Mar 1, 2022
- Intel Corporation
- Kristof Darmawikarta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-damascene zero-misalignment-via process for semiconductor pack...
- Patent number 11,264,307
- Issue date Mar 1, 2022
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polarization defined zero misalignment vias for semiconductor packa...
- Patent number 11,264,239
- Issue date Mar 1, 2022
- Intel Corporation
- Hiroki Tanaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electromigration resistant and profile consistent contact arrays
- Patent number 10,854,541
- Issue date Dec 1, 2020
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polarization defined zero misalignment vias for semiconductor packa...
- Patent number 10,453,812
- Issue date Oct 22, 2019
- Intel Corporation
- Hiroki Tanaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electromigration resistant and profile consistent contact arrays
- Patent number 10,431,537
- Issue date Oct 1, 2019
- Intel Corporation
- Srinivas Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-damascene zero-misalignment-via process for semiconductor pack...
- Patent number 10,403,564
- Issue date Sep 3, 2019
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package substrate first-level-interconnect architecture
- Patent number 10,121,679
- Issue date Nov 6, 2018
- Intel Corporation
- Aleksandar Aleksov
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SELECTIVE UNDERCUT FOR GLASS CORE SUBSTRATE BRIDGE FIRST LEVEL INTE...
- Publication number 20240355751
- Publication date Oct 24, 2024
- Intel Corporation
- Sanjay THARMARAJAH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AIR-GAP TRACES AND AIR-GAP EMBEDDED BRIDGE INTEGRATED IN GLASS INTE...
- Publication number 20240339381
- Publication date Oct 10, 2024
- Intel Corporation
- Hiroki TANAKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHOTONIC INTEGRATED CIRCUIT PACKAGES INCLUDING REPLACEABLE FIBER CO...
- Publication number 20240329339
- Publication date Oct 3, 2024
- Intel Corporation
- Jeremy Ecton
- G02 - OPTICS
Information Patent Application
CO-PACKAGING OF PHOTONIC & ELECTRONIC INTEGRATED CIRCUIT DIE
- Publication number 20240329333
- Publication date Oct 3, 2024
- Intel Corporation
- Robert May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING
- Publication number 20240243066
- Publication date Jul 18, 2024
- Intel Corporation
- Kristof DARMAWIKARTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO PRODUCE...
- Publication number 20240222259
- Publication date Jul 4, 2024
- Intel Corporation
- Haobo Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRO-OPTICAL CIRCUITS WITH MODULAR SWITCHABLE PHOTONIC INTERFACE
- Publication number 20240219644
- Publication date Jul 4, 2024
- Intel Corporation
- Suddhasattwa Nad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHOD FOR ELECTROLESS SURFACE FINISHING ON GLASS
- Publication number 20240194548
- Publication date Jun 13, 2024
- Intel Corporation
- Kristof Darmawikarta
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Microelectronic Assembly Including Interconnect Bridges with Throug...
- Publication number 20240186250
- Publication date Jun 6, 2024
- Intel Corporation
- Jeremy D. Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLY HAVING ANTIFERROMAGNETIC FILM STRUCTURE TH...
- Publication number 20240186270
- Publication date Jun 6, 2024
- Intel Corporation
- Srinivas V. Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING
- Publication number 20240178145
- Publication date May 30, 2024
- Intel Corporation
- Kristof DARMAWIKARTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHOTONIC INTEGRATED CIRCUIT PACKAGES INCLUDING SUBSTRATES WITH GLAS...
- Publication number 20240176070
- Publication date May 30, 2024
- Intel Corporation
- Jeremy Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGES INCLUDING A GLASS CORE WITH A FILTER ST...
- Publication number 20240178162
- Publication date May 30, 2024
- Intel Corporation
- Jeremy Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE WITH MICROFLUIDIC CHANNELS IN GLASS SUBSTRATES
- Publication number 20240162158
- Publication date May 16, 2024
- Intel Corporation
- Brandon C. Marin
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
PACKAGE ARCHITECTURE WITH GLASS CORE SUBSTRATE HAVING INTEGRATED IN...
- Publication number 20240128247
- Publication date Apr 18, 2024
- Intel Corporation
- Brandon C. Marin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE SUBSTRATE WITH DUAL DAMASCENE BASED SELF-ALIGNED VIAS
- Publication number 20240128181
- Publication date Apr 18, 2024
- Intel Corporation
- Jeremy Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID PLASMONIC WAVEGUIDE AND METHOD FOR HIGH DENSITY PACKAGING IN...
- Publication number 20240111095
- Publication date Apr 4, 2024
- Intel Corporation
- Hiroki Tanaka
- G02 - OPTICS
Information Patent Application
DIRECTLY COUPLED OPTICAL INTERPOSER
- Publication number 20240111090
- Publication date Apr 4, 2024
- Intel Corporation
- Robert A. May
- G02 - OPTICS
Information Patent Application
MULTICHIP IC DEVICES IN GLASS MEDIUM & INCLUDING AN INTERCONNECT BR...
- Publication number 20240113029
- Publication date Apr 4, 2024
- Intel Corporation
- Jeremy Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONICS PACKAGES WITH PHOTO-INTEGRATED GLASS INTERPOSER
- Publication number 20240112972
- Publication date Apr 4, 2024
- Intel Corporation
- Hiroki Tanaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID BONDING TECHNOLOGIES WITH THERMAL EXPANSION COMPENSATION STR...
- Publication number 20240113005
- Publication date Apr 4, 2024
- Intel Corporation
- Jeremy Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE FINISH WITH METAL DOME
- Publication number 20240105580
- Publication date Mar 28, 2024
- Intel Corporation
- Kristof DARMAWIKARTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROLYTIC SURFACE FINISH ARCHITECTURE
- Publication number 20240105575
- Publication date Mar 28, 2024
- Intel Corporation
- Jason M. GAMBA
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
DFR OVERHANG PROCESS FLOW FOR ELECTROLYTIC SURFACE FINISH FOR GLASS...
- Publication number 20240105576
- Publication date Mar 28, 2024
- Intel Corporation
- Kyle MCELHINNY
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
IC PACKAGE WITH LEDS
- Publication number 20240097079
- Publication date Mar 21, 2024
- Intel Corporation
- Brandon C. MARIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES WITH MIXED COPPER AND SOLDER INTERCONNEC...
- Publication number 20240096809
- Publication date Mar 21, 2024
- Intel Corporation
- Hiroki Tanaka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES
- Publication number 20240088121
- Publication date Mar 14, 2024
- Intel Corporation
- Srinivas PIETAMBARAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COPPER CLAD LAMINATE (CCL) FOR PLATING PADS WITHIN A GLASS CAVITY F...
- Publication number 20240087971
- Publication date Mar 14, 2024
- Intel Corporation
- Brandon C. MARIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAVITY-LESS INTERCONNECT COMPONENT ON GLASS CORE
- Publication number 20240071938
- Publication date Feb 29, 2024
- Intel Corporation
- Jeremy D. Ecton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE HAVING ONE OR MORE ELECTRICAL INTERCONNECTS
- Publication number 20240006298
- Publication date Jan 4, 2024
- Intel Corporation
- Suddhasattwa Nad
- H01 - BASIC ELECTRIC ELEMENTS

Hiroki Tanaka

Person

Patents Grantslast 30 patents

Subtractive etch resolution implementing a functional thin metal re...

Surface finishes with low RBTV for fine and mixed bump pitch archit...

Lithographic cavity formation to enable EMIB bump pitch scaling

Sacrificial dielectric for lithographic via formation to enable via...

Patch accommodating embedded dies having different thicknesses

Capacitors with nanoislands on conductive plates

Via structures having tapered profiles for embedded interconnect br...

Electromigration resistant and profile consistent contact arrays

Via-trace structures

Package architecture utilizing photoimageable dielectric (PID) for...

Surface finishes with low rBTV for fine and mixed bump pitch archit...

Via structures having tapered profiles for embedded interconnect br...

Lithographic cavity formation to enable EMIB bump pitch scaling

Electromigration resistant and profile consistent contact arrays

Sacrificial dielectric for lithographic via formation to enable via...

Dual-damascene zero-misalignment-via process for semiconductor pack...

Polarization defined zero misalignment vias for semiconductor packa...

Electromigration resistant and profile consistent contact arrays

Polarization defined zero misalignment vias for semiconductor packa...

Electromigration resistant and profile consistent contact arrays

Dual-damascene zero-misalignment-via process for semiconductor pack...

Package substrate first-level-interconnect architecture

Patents Applicationslast 30 patents

SELECTIVE UNDERCUT FOR GLASS CORE SUBSTRATE BRIDGE FIRST LEVEL INTE...

AIR-GAP TRACES AND AIR-GAP EMBEDDED BRIDGE INTEGRATED IN GLASS INTE...

PHOTONIC INTEGRATED CIRCUIT PACKAGES INCLUDING REPLACEABLE FIBER CO...

CO-PACKAGING OF PHOTONIC & ELECTRONIC INTEGRATED CIRCUIT DIE

LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING

METHODS, SYSTEMS, APPARATUS, AND ARTICLES OF MANUFACTURE TO PRODUCE...

ELECTRO-OPTICAL CIRCUITS WITH MODULAR SWITCHABLE PHOTONIC INTERFACE

APPARATUS AND METHOD FOR ELECTROLESS SURFACE FINISHING ON GLASS

Microelectronic Assembly Including Interconnect Bridges with Throug...

MICROELECTRONIC ASSEMBLY HAVING ANTIFERROMAGNETIC FILM STRUCTURE TH...

LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING

PHOTONIC INTEGRATED CIRCUIT PACKAGES INCLUDING SUBSTRATES WITH GLAS...

INTEGRATED CIRCUIT PACKAGES INCLUDING A GLASS CORE WITH A FILTER ST...

PACKAGE ARCHITECTURE WITH MICROFLUIDIC CHANNELS IN GLASS SUBSTRATES

PACKAGE ARCHITECTURE WITH GLASS CORE SUBSTRATE HAVING INTEGRATED IN...

PACKAGE SUBSTRATE WITH DUAL DAMASCENE BASED SELF-ALIGNED VIAS

HYBRID PLASMONIC WAVEGUIDE AND METHOD FOR HIGH DENSITY PACKAGING IN...

DIRECTLY COUPLED OPTICAL INTERPOSER

MULTICHIP IC DEVICES IN GLASS MEDIUM & INCLUDING AN INTERCONNECT BR...

MICROELECTRONICS PACKAGES WITH PHOTO-INTEGRATED GLASS INTERPOSER

HYBRID BONDING TECHNOLOGIES WITH THERMAL EXPANSION COMPENSATION STR...

SURFACE FINISH WITH METAL DOME

ELECTROLYTIC SURFACE FINISH ARCHITECTURE

DFR OVERHANG PROCESS FLOW FOR ELECTROLYTIC SURFACE FINISH FOR GLASS...

IC PACKAGE WITH LEDS

MICROELECTRONIC ASSEMBLIES WITH MIXED COPPER AND SOLDER INTERCONNEC...

PATCH ACCOMMODATING EMBEDDED DIES HAVING DIFFERENT THICKNESSES

COPPER CLAD LAMINATE (CCL) FOR PLATING PADS WITHIN A GLASS CAVITY F...

CAVITY-LESS INTERCONNECT COMPONENT ON GLASS CORE

SUBSTRATE HAVING ONE OR MORE ELECTRICAL INTERCONNECTS