BACKGROUND
For the past several decades, scaling of features in integrated circuits (ICs) has been a driving force behind an ever-growing semiconductor industry and emerging applications in fields such as big data, artificial intelligence, mobile communications, and autonomous driving. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize fabrication and performance of each component (e.g., of each transistor) is becoming increasingly significant.
Parallel to optimizations at the transistor level, advanced IC packaging landscape is rapidly evolving to accommodate performance expectations and requirements of shrinking transistor size. Multiple IC dies are now commonly coupled together in a multi-die IC package to integrate features or functionality and to facilitate connections to other components, such as package substrates. For example, IC packages may include an embedded multi-die interconnect bridge (EMIB) for coupling two or more IC dies.
Integration of multiple dies in a single IC package has tremendous benefits but adds additional complexities due to placing materials with different material properties in close proximity to one another. When an IC package undergoes multiple processing steps involving various temperatures and pressure loads, individual materials within the package may behave differently from one another, resulting in out of plane deformation of various layers, known as “package warpage.” One way to address package warpage is to use stiffer cores to which different IC dies are attached. Recently, glass cores have been explored as alternatives to organic resin-based cores (e.g., cores based on using Ajinomoto Build-up Film (ABF)). Glass is considered more rigid than organic resin-based materials and has several advantages such as excellent thermal properties, low coefficient of thermal expansion (CTE), high electrical insulation, chemical resistance, optical transparency, and compatibility with advances semiconductor properties. However, a major challenge for widespread adoption of glass cores is the fact that glass is highly susceptible to damage due to mechanical and/or thermal stresses.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings.
FIG. 1 is a schematic side, cross-sectional view of one example microelectronic assembly, according to some embodiments of the present disclosure.
FIG. 2 is a schematic side, cross-sectional view of another example microelectronic assembly, according to some embodiments of the present disclosure.
FIG. 3 illustrates a glass panel during singulation.
FIGS. 4A-4B illustrate approximate locations of edge features in a glass core, according to some embodiments of the present disclosure.
FIG. 5 is a schematic side, cross-sectional view of one example microelectronic assembly with an edge protection coating, according to some embodiments of the present disclosure.
FIGS. 6A-6C provide cross-sectional side views of glass cores illustrating variations in the extent of edge protection coatings, according to some embodiments of the present disclosure.
FIGS. 7A-7C illustrate a process of healing cracks using an edge protection coating with a crack-healing material, according to some embodiments of the present disclosure.
FIGS. 8A-8C provide cross-sectional side views illustrating variations in edge shapes of glass cores, according to some embodiments of the present disclosure.
FIGS. 9A-9B provide cross-sectional side views illustrating variations in edge shapes of build-up layers, according to some embodiments of the present disclosure.
FIGS. 10A-10C provide cross-sectional side views illustrating variations in edge shapes of edge protection coatings, according to some embodiments of the present disclosure.
FIGS. 11A-11H provide cross-sectional side views illustrating portions of the microelectronic assemblies with variations in combinations of glass cores and build-up layers with different edge shapes, according to some embodiments of the present disclosure.
FIGS. 12A-12G provide cross-sectional side views illustrating portions of the microelectronic assemblies with variations in combinations of glass cores, build-up layers, and edge protection coatings with different edge shapes where the edge protection coatings are partial chamfered coatings, according to some embodiments of the present disclosure.
FIGS. 13A-13H provide cross-sectional side views illustrating portions of the microelectronic assemblies with variations in combinations of glass cores, build-up layers, and edge protection coatings with different edge shapes where the edge protection coatings are rounded full coatings, according to some embodiments of the present disclosure.
FIGS. 14A-14H provide cross-sectional side views illustrating portions of the microelectronic assemblies with variations in combinations of glass cores, build-up layers, and edge protection coatings with different edge shapes where the edge protection coatings are thin-film coatings, according to some embodiments of the present disclosure.
FIGS. 15A-15H provide cross-sectional side views illustrating portions of the microelectronic assemblies with variations in combinations of glass cores, build-up layers, and edge protection coatings with different edge shapes where the edge protection coatings are partial rounded coatings, according to some embodiments of the present disclosure.
FIGS. 16A-16H provide cross-sectional side views illustrating portions of the microelectronic assemblies with variations in combinations of glass cores, build-up layers, and edge protection coatings with different edge shapes where the edge protection coatings are full straight edge coatings, according to some embodiments of the present disclosure.
FIGS. 17A-17G provide cross-sectional side views illustrating portions of the microelectronic assemblies (e.g., the microelectronic assemblies 100) with variations in combinations of glass cores 110, build-up layers 210, and edge protection coatings 232 with different edge shapes where the edge protection coatings 232 are full chamfered coatings, according to some embodiments of the present disclosure.
FIGS. 18A-18H provide cross-sectional side views illustrating portions of the microelectronic assemblies with variations in combinations of glass cores, build-up layers, and edge protection coatings with different edge shapes where the edge protection coatings are partial straight edge coatings, according to some embodiments of the present disclosure.
FIGS. 19A-19B provide top-down and cross-sectional side views of a glass core illustrating an edge feature in the form of a frame, according to some embodiments of the present disclosure.
FIGS. 20A-20B provide top-down and cross-sectional side views of a glass core to which a thermal treatment in the form of heating and cooling glass edges has been applied, according to some embodiments of the present disclosure.
FIGS. 21A-21B provide top-down and cross-sectional side views of a glass core to which a thermal treatment in the form of laser peening has been applied, according to some embodiments of the present disclosure.
FIGS. 22A-22B provide top-down and cross-sectional side views of a glass core to which a thermal treatment by means of an ultrafast laser has been applied, according to some embodiments of the present disclosure.
FIGS. 23A-23B provide top-down and cross-sectional side views of a glass core to which a chemical treatment has been applied, according to some embodiments of the present disclosure.
FIG. 24 is a top view of a wafer and dies that may be included in a microelectronic assembly with a glass core in accordance with any of the embodiments disclosed herein, according to some embodiments of the present disclosure.
FIG. 25 is a side, cross-sectional view of an IC device that may be included in a microelectronic assembly with a glass core in accordance with any of the embodiments disclosed herein, according to some embodiments of the present disclosure.
FIG. 26 is a side, cross-sectional view of an IC device assembly that may include a glass core in accordance with any of the embodiments disclosed herein, according to some embodiments of the present disclosure.
FIG. 27 is a block diagram of an example communication device that may include a microelectronic assembly with a glass core in accordance with any of the embodiments disclosed herein, according to some embodiments of the present disclosure.
DETAILED DESCRIPTION
As mentioned above, a major challenge for widespread adoption of glass cores is the fact that glass is highly susceptible to damage due to mechanical and/or thermal stresses. One source of mechanical and thermal stresses in glass is singulation process (sometimes referred to as “dicing” or “cutting”) that takes place during manufacturing of glass cores. Singulation is a process in which a cutting tool (e.g., a glass cutter, a diamond blade, or a saw) applies mechanical force to the surface of a glass panel in order to separate (e.g., dice or cut) the panel into individual glass units having a smaller form factor than the panel. The mechanical force applied by the cutting tool may create a localized stress concentration (e.g., regions of higher stress) at or near the surfaces where the cutting tool contacts the glass, e.g., at or near the edges of the individual glass units, where, as used herein, the term “edge” refers to a side/sidewall that is between top and the bottom faces of a glass unit, a glass core, or glass panel. Because glass is a brittle material characterized by its lack of ductility (e.g., characterized by its limited ability to undergo significant plastic deformation before fracturing), localized stress concentration often leads to formation of cracks at the edges of singulated glass units. Besides imposing mechanical stress onto glass, singulation can also generate thermal stress due to friction between the cutting tool and glass, heating up the surface being cut. The heat can cause localized expansion and contraction of glass, further promoting crack formation and propagation.
Singulation is not the only source of stress and damage that may affect glass cores. Presence of materials with different CTEs on top and/or on the bottom of glass cores (e.g., metals of conductive pathways and/or dielectric materials of build-up layers) adds to the stresses in glass (such stresses referred to as “CTE mismatch-induced stresses”), further exacerbating the problem of crack formation. Even if cracks don't form immediately during singulation, cutting of brittle materials like glass often results in individual glass units with edges that are rough, jagged, or otherwise uneven. Repeated thermal cycling during operation of microelectronic assemblies that include glass cores with such edges can gradually weaken the glass surface due to CTE mismatch-induced stresses, leading to formation of cracks at that time. Furthermore, even before singulation, glass may have tiny surface flaws or defects, which can act as initiation points for crack formation, with additional mechanical and/or thermal stresses increasing the severity of crack growth.
Once cracks start to form, they tend to propagate through glass, with additional mechanical and/or thermal stresses increasing the severity of crack propagation. In particular, the stress concentration at the edges of the glass units encourages the cracks to extend further into glass, and the inherent brittleness of glass makes it particularly susceptible to crack propagation. Propagation of cracks may even cause a glass volume to split into two halves around a plane parallel to the top/bottom surfaces of the glass volume and being about in the middle of the glass volume, one half being the bottom half and the other half being the top half of what is supposed to be a single structure.
As the foregoing illustrates, crack formation and propagation in glass compromises the structural integrity of glass, making microelectronic assemblies with glass cores particularly prone to failure over time. Embodiments of the present disclosure relate to various techniques, as well as to related devices and methods, for alleviating (e.g., mitigating or reducing) crack formation and propagation in glass. In particular, embodiments of the present disclosure are based on providing various edge features during or after singulation of a glass panel into individual glass units. Because these edge features are detectable after singulation, they may be referred to as “post-singulation” edge features. The individual glass units can serve as glass cores of microelectronic assemblies, and the edge features can help mitigate or reduce crack formation and/or propagation in glass cores. As used herein, an “edge feature” refers to any feature located at or near an edge of a glass core (e.g., of a glass unit after singulation). For example, in one aspect of the present disclosure, a microelectronic assembly includes a glass core (e.g., a layer of glass including a rectangular prism volume) having a first face, a second face opposite the first face, and an edge between an end of the first face and an end of the second face, and further includes a protection coating on the edge. In another aspect, a microelectronic assembly includes a glass core as in the first aspect and further includes a frame around the edge. In yet another aspect, a microelectronic assembly includes a glass core with edges that have undergone thermal and/or chemical treatment.
Integration of layers of different materials (e.g., multiple dies, redistribution layers, package substrates) in a single IC package or a microelectronic assembly is challenging due to package warpage, among others. Providing IC packages or microelectronic assemblies with glass cores having one or more edge features as described herein may help. Various ones of the embodiments disclosed herein may help achieve reliable integration of multiple layers of different materials within a single microelectronic assembly at a lower cost and/or with greater design flexibility, relative to conventional approaches. Various ones of the microelectronic assemblies disclosed herein may exhibit reduced warpage, relative to microelectronic assemblies without glass cores. The microelectronic assemblies disclosed herein may be particularly advantageous for small and low-profile applications in computers, tablets, industrial robots, and consumer electronics (e.g., wearable devices).
In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.
Any of the features discussed with reference to any of accompanying drawings herein may be combined with any other features to form a microelectronic assembly 100, a glass core 110, an IC device 1600, an IC device assembly 1700, or a communication device 1800, as appropriate. For convenience, the phrase “dies 114” may be used to refer to a collection of dies 114-1, 114-2, and so on, etc. A collection of drawings labeled with different letters may be referred to without the letters, e.g., a collection of FIGS. 6A-6C may be referred to as “FIG. 6,” a collection of FIGS. 7A-7C may be referred to as “FIG. 7,” etc. A number of elements of the drawings with same reference numerals may be shared between different drawings; for ease of discussion, a description of these elements provided with respect to one of the drawings is not repeated for the other drawings, and these elements may take the form of any of the embodiments disclosed herein. To not clutter the drawings, if multiple instances of certain elements are illustrated, only some of the elements may be labeled with a reference numeral (e.g., a plurality of conductive contacts 122 are shown in FIG. 1 but only one of the them is labeled with a reference numeral). Also to not clutter the drawings, not all reference numerals shown in one of the drawings are shown in other similar drawings.
The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration and may not reflect real-life process limitations which may cause various features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers. There may be other defects not listed here but that are common within the field of semiconductor device fabrication and packaging. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of a glass core with one or more edge features as described herein.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y. When used to describe a location of an element, the phrase “between X and Y” represents a region that is spatially between element X and element Y. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−10%, e.g., within +/−5% or within +/−2%, of the exact orientation.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die.” Furthermore, the terms “chip,” “chiplet,” “die,” and “IC die” may be used interchangeably herein.
Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “a dielectric material” may include one or more dielectric materials or “an insulator material” may include one or more insulator materials. The terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. The term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide. The term “insulating” and variations thereof (e.g., “insulative” or “insulator”) means “electrically insulating,” the term “conducting” and variations thereof (e.g., “conductive” or “conductor”) means “electrically conducting,” unless otherwise specified. With reference to optical signals and/or devices, components and elements that operate on or using optical signals, the term “conducting” can also mean “optically conducting.” The term “insulating material” refers to solid materials (and/or liquid materials that solidify after processing as described herein) that are substantially electrically nonconducting. They may include, as examples and not as limitations, organic polymers and plastics, and inorganic materials such as ionic crystals, porcelain, glass, silicon and alumina or a combination thereof. They may include dielectric materials, high polarizability materials, and/or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Further examples of insulating materials are underfills and molds or mold-like materials used in packaging applications, including for example, materials used in organic interposers, package supports and other such components.
FIG. 1 is a schematic side, cross-sectional view of one example microelectronic assembly 100 in which a glass core with one or more edge features as described herein may be implemented, according to some embodiments of the present disclosure. The microelectronic assembly 100 may include a substrate 107 with a double-sided bridge die 114-1 in a cavity 119 in the substrate 107, the die 114-1 may be electrically coupled to a conductive pathway, e.g., a conductive trace 108A or a conductive via 108B, in a metal layer N-1 of the substrate 107 that is beneath a bottom of the cavity 119. The substrate 107 may include a dielectric material 112 (e.g., a first dielectric material layer 112A and a second dielectric material layer 112B, as shown, together referred to as “one or more layers of the dielectric material 112”) and a conductive material 108 arranged in the one or more layers of the dielectric material 112 to provide conductive pathways (e.g., conductive traces 108A and conductive vias 108B) through the substrate 107, as well as to provide conductive pads and contacts. The substrate 107 may include a first surface 120-1 and an opposing second surface 120-2. The die 114-1 may be surrounded by the dielectric material 112 of the substrate 107. The die 114-1 may include a bottom face (e.g., the surface facing towards the first surface 120-1) with first conductive contacts 122, an opposing top face (e.g., the surface facing towards the second surface 120-2) with second conductive contacts 124, and through-silicon vias (TSVs) 125 coupling respective first and second conductive contacts 122, 124. In some embodiments, a pitch of the first conductive contacts 122 on the first die 114-1 maybe between 25 microns and 250 microns. As used herein, pitch is measured center-to-center (e.g., from a center of a conductive contact to a center of an adjacent conductive contact). In some embodiments, a pitch of the second conductive contacts 124 on the first die 114-1 maybe between 25 microns and 100 microns. The dies 114-2, 114-3 may include a set of conductive contacts 122 on the bottom face of the die (e.g., the surface facing towards the first surface 120-1). The die 114 may include other conductive pathways (e.g., including lines and vias) and/or to other circuitry (not shown) coupled to the respective conductive contacts (e.g., conductive contacts 122, 124) on the surface of the die 114. As used herein, the terms “die,” “microelectronic component,” and similar variations may be used interchangeably. As used herein, the terms “interconnect component,” “bridge die,” and similar variations may be used interchangeably. The bridge die 114-1 may be electrically coupled to dies 114-2, 114-3 by die-to-die (DTD) interconnects 130 at a second surface 120-2. In particular, conductive contacts 124 on a top face of the die 114-1 may be coupled to conductive contacts 122 on a bottom face of dies 114-2, 114-3 by conductive vias 108B through the second dielectric material layer 112B.
As used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components (e.g., part of a conductive interconnect); conductive contacts may be recessed in, flush with, or extending away (e.g., having a pillar shape) from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket, or portion of a conductive line or via). In a general sense, an “interconnect” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, facilitating communication of electrical signals between them; an optical interconnect provides optical connectivity between two optical components, facilitating communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are comprised in the term “interconnect.” The nature of the interconnect being described is to be understood herein with reference to the signal medium associated therewith. Thus, when used with reference to an electronic device, such as an IC that operates using electrical signals, the term “interconnect” describes any element formed of a conductive material for providing electrical connectivity to one or more elements associated with the IC or/and between various such elements. In such cases, the term “interconnect” may refer to both conductive traces (also sometimes referred to as “metal traces,” “lines,” “metal lines,” “wires,” “metal wires,” “trenches,” or “metal trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). Sometimes, conductive traces and vias may be referred to as “metal traces” and “metal vias”, respectively, to highlight the fact that these elements include conductive materials such as metals. Likewise, when used with reference to a device that operates on optical signals as well, such as a photonic IC (PIC), “interconnect” may also describe any element formed of a material that is optically conductive for providing optical connectivity to one or more elements associated with the PIC. In such cases, the term “interconnect” may refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fiber, optical splitters, optical combiners, optical couplers, and optical vias.
The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive pathways formed through the insulating material. In some embodiments, the insulating material of a die 114 may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, polyimide materials, glass reinforced epoxy matrix materials, or a low-k or ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymeric dielectrics, photo-imageable dielectrics, and/or benzocyclobutene-based polymers). In some embodiments, the insulating material of a die 114 may include a semiconductor material, such as silicon, germanium, or a III-V material (e.g., gallium nitride), and one or more additional materials. For example, an insulating material may include silicon oxide or silicon nitride. The conductive pathways in a die 114 may include conductive traces and/or conductive vias, and may connect any of the conductive contacts in the die 114 in any suitable manner (e.g., connecting multiple conductive contacts on a same surface or on different surfaces of the die 114). Example structures that may be included in the dies 114 disclosed herein are discussed below with reference to the IC device 1600. The conductive pathways in the dies 114 may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable. In some embodiments, the die 114 is a wafer. In some embodiments, the die 114 is a monolithic silicon, a fan-out or fan-in package die, or a die stack (e.g., wafer stacked, die stacked, or multi-layer die stacked).
In some embodiments, the die 114 may include conductive pathways to route power, ground, and/or signals to/from other dies 114 included in the microelectronic assembly 100. For example, the die 114-1 may include TSVs 125, including a conductive via, such as a metal via, isolated from the surrounding silicon or other semiconductor material by a barrier oxide), or other conductive pathways through which power, ground, and/or signals may be transmitted between the package substrate 102 and one or more dies 114 “on top” of the die 114-1 (e.g., in the embodiment of FIG. 1, the dies 114-2 and/or 114-3). In some embodiments, the die 114-1 may not route power and/or ground to the dies 114-2 and 114-3; instead, the dies 114-2, 114-3 may couple directly to power and/or ground lines in the package substrate 102 by substrate-to-package substrate (STPS) interconnects 150, conductive pathways provided by the conductive material 108 in the substrate 107, and die-to-substrate (DTS) interconnects 140. In some embodiments, the die 114-1 may be thicker than the dies 114-2, 114-3. In some embodiments, the die 114-1 may be a memory device or a high frequency serializer and deserializer (SerDes), such as a Peripheral Component Interconnect (PCI) express. In some embodiments, the die 114-1 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor. In some embodiments, the die 114-2 and/or the die 114-3 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor. In some embodiments, the die 114 may be as described below with reference to the die 1502 of FIG. 24.
The dielectric material 112 of the substrate 107 may be formed in layers (e.g., at least a first dielectric material layer 112A and a second dielectric material layer 112B). In some embodiments, the dielectric material 112 may include an organic material, such as an organic build-up film. In some embodiments, the dielectric material 112 may include a ceramic, an epoxy film having filler particles therein, glass, an inorganic material, or combinations of organic and inorganic materials, for example. In some embodiments, the conductive material 108 may include a metal (e.g., copper). In some embodiments, the substrate 107 may include layers of dielectric material 112/conductive material 108, with lines/traces/pads/contacts (e.g., conductive traces 108A) of conductive material 108 in one layer electrically coupled to lines/traces/pads/contacts (e.g., conductive traces 108A) of conductive material 108 in an adjacent layer by vias (e.g., 108B) of the conductive material 108 extending through the dielectric material 112. Conductive traces 108A may be referred to herein as “conductive lines,” “conductive elements,” “conductive pads,” or “conductive contacts.” A substrate 107 including such layers may be formed using a printed circuit board (PCB) fabrication technique, for example.
An individual layer of dielectric material 112 (e.g., a first dielectric material layer 112A) may include a cavity 119 and the bridge die 114-1 may be at least partially nested in the cavity 119. The bridge die 114-1 may be surrounded by (e.g., embedded in) a next individual layer of dielectric material 112 (e.g., a second dielectric material layer 112B). In some embodiments, a cavity 119 is tapered, narrowing towards a bottom face of the cavity 119 (e.g., the surface towards the first surface 120-1 of the substrate 107). A cavity 119 may be indicated by a seam between the dielectric material 112A and the dielectric material 112B. As shown in FIG. 1, in cases where the bridge die 114-1 is partially nested in a cavity 119, a top face of the bridge die 114-1 may extend above a top face of dielectric material 112A. In cases where the bridge die 114-1 is fully nested in a cavity 119 (not shown), a top face of the bridge die 114-1 may be planar with or below a top face of dielectric material 112A.
A substrate 107 may include N layers of conductive material 108, where N is an integer greater than or equal to one. In FIG. 1, the layers are labeled in descending order from the second surface 120-2 (e.g., the top face) of the substrate 107 (e.g., layer N, layer N-1, layer N-2, etc.). In particular, as shown in FIG. 1, a substrate 107 may include four metal layers (e.g., N, N-1, N-2, and N-3). The N metal layer may include conductive contacts 121 at the second surface 120-2 of the substrate 107 that are coupled to conductive contacts 122 at bottom faces of the die 114-2, 114-3 by DTS interconnects 140. The N-2 metal layer may include conductive traces 108A having a top face (e.g., the surface facing towards the second surface 120-2 of the substrate 107), an opposing bottom face (e.g., the surface facing towards the first surface 120-1 of the substrate 107), and lateral surfaces extending between the top and bottom faces of the conductive traces 108A. A substrate 107 may further include an N-1 metal layer above the N-2 metal layer and below the N metal layer, where a portion of the N-1 metal layer includes a metal ring 118 exposed at a perimeter of the bottom of the cavity 119. The metal ring 118 may be coplanar with the conductive traces 108A of the N-1 metal layer and may be proximate to the edges of the cavity 119, as shown.
Although a particular number and arrangement of layers of dielectric material 112/conductive material 108 are shown in various ones of the accompanying figures, these particular numbers and arrangements are simply illustrative, and any desired number and arrangement of dielectric material 112/conductive material 108 may be used. Further, although a particular number of layers are shown in the substrate 107 (e.g., four layers), these layers may represent only a portion of the substrate 107, for example, further layers may be present (e.g., layers N-4, N-5, N-6, etc.).
As shown in FIG. 1, the substrate 107 may further include a glass core 110 with TGVs 115 and further layers 111 may be present below the glass core 110 and coupled to a package substrate 102 by interconnects 150. As used herein, the term “glass core” refers to a layer (e.g., a glass layer) or a structure (e.g., a portion of a glass layer) of any glass material such as quartz, silica, fused silica, silicate glass (e.g., borosilicate, aluminosilicate, alumino-borosilicate), soda-lime glass, soda-lime silica, borofloat glass, lead borate glass, photosensitive glass, non-photosensitive glass, or ceramic glass. In particular, the glass core 110 may be bulk glass or a solid volume/layer of glass, as opposed to, e.g., materials that may include particles of glass, such as glass fiber reinforced polymers (e.g., substrates/boards constructed of glass fibers and an epoxy binder). Such glass materials are typically non-crystalline, often transparent, amorphous solids. In some embodiments, the glass core 110 may be an amorphous solid glass layer. In some embodiments, the glass core 110 may include a material comprising silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass core 110 may include a material, e.g., any of the materials described above, with a weight percentage of silicon being at least about 0.5%, e.g., between about 0.5% and 50%, between about 1% and 48%, or at least about 23%. For example, if the glass core 110 is fused silica, the weight percentage of silicon may be about 47%. In some embodiments, the glass core 110 may include a material having at least 23% silicon and/or at least 26% oxygen by weight, and, in some further embodiments, the glass core 110 may further include at least 5% aluminum by weight. In some embodiments, the glass core 110 may include any of the materials described above and may further include one or more additives such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. In some embodiments, the glass core 110 may be a layer of glass that does not include an organic adhesive or an organic material. The glass core 110 may be distinguished from, for example, the “prepreg” or “RF4” core of a PCB substrate which typically includes glass fibers embedded in a resinous organic material such as an epoxy. In such traditional cores/substrates including glass fibers and epoxy, the diameter of the glass fibers is generally in the range of 5 micron to 200 micron. In contract, the glass core 110 may be a layer of glass that is about 10 millimeters on a side to about 250 millimeters on a side (e.g., 10 millimeters×10 millimeters to 250 millimeters×250 millimeters). In some embodiments, a cross-section of the glass core 110 in an x-z plane, a y-z plane, and/or an x-y plane of an example coordinate system 105, shown in FIG. 1, may be substantially rectangular (axes shown in subsequent drawings refer to the axes of the coordinate system 105). In such embodiments, in the top-down view of the glass core 110 (e.g., the x-y plane of the coordinate system 105), the glass core 110 may have a first length in a range of 10 millimeters to 250 millimeters, and a second length in a range of 10 millimeters to 250 millimeters, the first length perpendicular to the second length. A thickness of the glass core 110 (e.g., a dimension measured along the z-axis of the coordinate system 105) may be in a range of about 50 micron to 1.4 millimeters. In some embodiments, the glass core 110 may be a glass core substrate, where the glass core substrate has a thickness in a range of about 50 microns to 1.4 millimeters. In some embodiments, the glass core 110 may be a layer of glass comprising a rectangular prism volume. In some such embodiments, the rectangular prism volume may have a first side and a second side perpendicular to the first side, the first side having a length in a range of 10 millimeters to 250 millimeters and the second side having a length in a range of 10 millimeters to 250 millimeters. In some embodiments, the glass core 110 may be a rectangular prism volume with sections (e.g., vias) removed and filled with other materials (e.g., metal) e.g., the TGVs 115. In some embodiments, the glass core 110 may be a layer of glass having a thickness in a range of 50 microns to 1.4 millimeters, a first length in a range of 10 millimeters to 250 millimeters, and a second length in a range of 10 millimeters to 250 millimeters, the first length perpendicular to the second length.
In some implementations, together, the substrate 107, including the glass core 110, and the dies 114 may be referred to as a “a multi-layer die subassembly 104.” The glass core 110 may provide mechanical stability to the multi-layer die subassembly 104, the substrate 107, and/or the microelectronic assembly 100. The glass core 110 may reduce warpage and may provide a more robust surface for attachment of the multi-layer die subassembly 104 to a package substrate 102 or other substrate (e.g., an interposer or a circuit board).
In some implementations, together, the dielectric material 112 of the substrate 107 and the glass core 110 may be referred to as a “multi-layer glass substrate.” In some such embodiments, the multi-layer glass substrate may be a coreless substrate. In some such embodiments, the glass core 110 may be a glass layer having a thickness in a range of about 25 microns to 50 microns. In some embodiments, the further layers 111 may also be part of the multi-layer glass substrate.
The TGVs 115 may be vias extending between a first side and a second side of the glass core 110 (e.g., between the bottom face and the top face of the glass core 110), the vias including any appropriate conductive material, e.g., a metal such as copper, silver, nickel, gold, aluminum, or other metals or alloys, for example. The TGVs 115 may be formed using any suitable process, including, for example, a direct laser drilling or laser-induced deep etching process. In some embodiments, the TGVs 115 disclosed herein may have a pitch between 50 microns and 500 microns, e.g., as measured from a center of one TGV 115 to a center of an adjacent TGV 115. The TGVs 115 may have any suitable size and shape. In some embodiments, the TGVs 115 may have a circular, rectangular, or other shaped cross-section. In some embodiments, at least some of the TGVs 115 may have an hourglass shape, e.g., as shown in FIG. 2. In some embodiments, at least some of the TGVs 115 may taper down from one face of the glass core 110 to another, e.g., from the top face of the glass core 110 to the bottom face of the glass core 110.
The substrate 107 (e.g., further layers 111) may be coupled to a package substrate 102 by STPS interconnects 150. In particular, the top face of the package substrate 102 may include a set of conductive contacts 146. Conductive contacts 144 on the bottom face of the substrate 107 may be electrically and mechanically coupled to the conductive contacts 146 on the top face of the package substrate 102 by the STPS interconnects 150. The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways to route power, ground, and signals through the dielectric material (e.g., including conductive traces and/or conductive vias, as shown). In some embodiments, the insulating material of the package substrate 102 may be a dielectric material, such as an organic dielectric material, a fire retardant grade 4 material (FR-4), bismaleimide triazine (BT) resin, polyimide materials, glass reinforced epoxy matrix materials, organic dielectrics with inorganic fillers or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In particular, when the package substrate 102 is formed using standard PCB processes, the package substrate 102 may include FR-4, and the conductive pathways in the package substrate 102 may be formed by patterned sheets of copper separated by build-up layers of the FR-4. The conductive pathways in the package substrate 102 may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable. In some embodiments, the package substrate 102 may be formed using a lithographically defined via packaging process. In some embodiments, the package substrate 102 may be manufactured using standard organic package manufacturing processes, and thus the package substrate 102 may take the form of an organic package. In some embodiments, the package substrate 102 may be a set of redistribution layers formed on a panel carrier by laminating or spinning on a dielectric material, and creating conductive vias and lines by laser drilling and plating. In some embodiments, the package substrate 102 may be formed on a removable carrier using any suitable technique, such as a redistribution layer technique. Any method known in the art for fabrication of the package substrate 102 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.
In some embodiments, the package substrate 102 may be a lower density medium and the die 114 may be a higher density medium or have an area with a higher density medium. As used herein, the term “lower density” and “higher density” are relative terms indicating that the conductive pathways (e.g., including conductive interconnects, conductive lines, and conductive vias) in a lower density medium are larger and/or have a greater pitch than the conductive pathways in a higher density medium. In some embodiments, a higher density medium may be manufactured using a modified semi-additive process or a semi-additive build-up process with advanced lithography (with small vertical interconnect features formed by advanced laser or lithography processes), while a lower density medium may be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process using etch chemistry to remove areas of unwanted copper, and with coarse vertical interconnect features formed by a standard laser process). In other embodiments, the higher density medium may be manufactured using semiconductor fabrication process, such as a single damascene process or a dual-damascene process. In some embodiments, additional dies may be disposed on the top face of the dies 114-2, 114-3. In some embodiments, additional components may be disposed on the top face of the dies 114-2, 114-3. Additional passive components, such as surface-mount resistors, capacitors, and/or inductors, may be disposed on the top face or the bottom face of the package substrate 102, or embedded in the package substrate 102.
The microelectronic assembly 100 of FIG. 1 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend between the substrate 107 and the package substrate 102 around the associated STPS interconnects 150. In some embodiments, the underfill material 127 may extend between different ones of the top level dies 114-2, 114-3 and the top face of the substrate 107 around the associated DTS interconnects 140 and between the bridge die 114-1 and the top level dies 114-2, 114-3 around the DTD interconnects 130. The underfill material 127 may be an insulating material, such as an appropriate epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, non-conductive film (NCF), or molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that assists with soldering the multi-layer die subassembly 104 to the package substrate 102 when forming the STPS interconnects 150, and then polymerizes and encapsulates the STPS interconnects 150. The underfill material 127 may be selected to have a CTE that may mitigate or minimize the stress between the substrate 107 and the package substrate 102 arising from uneven thermal expansion in the microelectronic assembly 100. In some embodiments, the CTE of the underfill material 127 may have a value that is intermediate to the CTE of the package substrate 102 (e.g., the CTE of the dielectric material of the package substrate 102) and a CTE of the dies 114 and/or dielectric material 112 of the substrate 107.
The STPS interconnects 150 disclosed herein may take any suitable form. In some embodiments, a set of STPS interconnects 150 may include solder (e.g., solder bumps or balls that are subject to a thermal reflow to form the STPS interconnects 150), for example, as shown in FIG. 1, the STPS interconnects 150 may include solder between a conductive contacts 144 on a bottom face of the substrate 107 and a conductive contact 146 on a top face of the package substrate 102. In some embodiments, a set of STPS interconnects 150 may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. An anisotropic conductive material may include conductive materials dispersed in a non-conductive material.
The DTD interconnects 130 disclosed herein may take any suitable form. The DTD interconnects 130 may have a finer pitch than the STPS interconnects 150 in a microelectronic assembly. In some embodiments, the dies 114 on either side of a set of DTD interconnects 130 may be unpackaged dies, and/or the DTD interconnects 130 may include small conductive bumps (e.g., copper bumps). The DTD interconnects 130 may have too fine a pitch to couple to the package substrate 102 directly (e.g., too fine to serve as DTS interconnects 140 or STPS interconnects 150). In some embodiments, a set of DTD interconnects 130 may include solder. In some embodiments, a set of DTD interconnects 130 may include an anisotropic conductive material, such as any of the materials discussed above. In some embodiments, the DTD interconnects 130 may be used as data transfer lanes, while the STPS interconnects 150 may be used for power and ground lines, among others. In some embodiments, some or all of the DTD interconnects 130 in a microelectronic assembly 100 may be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or plated interconnects). In such embodiments, the DTD interconnect 130 may be bonded together (e.g., under elevated pressure and/or temperature) without the use of intervening solder or an anisotropic conductive material. Any of the conductive contacts disclosed herein (e.g., the conductive contacts 122, 124, 144, and/or 146) may include bond pads, solder bumps, conductive posts, or any other suitable conductive contact, for example. In some embodiments, some or all of the DTD interconnects 130 and/or the DTS interconnects 140 in a microelectronic assembly 100 may be solder interconnects that include a solder with a higher melting point than a solder included in some or all of the STPS interconnects 150. For example, when the DTD interconnects 130 and the DTS interconnects 140 in a microelectronic assembly 100 are formed before the STPS interconnects 150 are formed, solder-based DTD interconnects 130 and DTS interconnects 140 may use a higher-temperature solder (e.g., with a melting point above 200 degrees Celsius), while the STPS interconnects 150 may use a lower-temperature solder (e.g., with a melting point below 200 degrees Celsius). In some embodiments, a higher-temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, a lower-temperature solder may include tin and bismuth (e.g., eutectic tin bismuth) or tin, silver, and bismuth. In some embodiments, a lower-temperature solder may include indium, indium and tin, or gallium.
In the microelectronic assemblies 100 disclosed herein, some or all of the DTS interconnects 140 and the STPS interconnects 150 may have a larger pitch than some or all of the DTD interconnects 130. DTD interconnects 130 may have a smaller pitch than STPS interconnects 150 due to the greater similarity of materials in the different dies 114 on either side of a set of DTD interconnects 130 than between the substrate 107 and the top level dies 114-2, 114-3 on either side of a set of DTS interconnects 140, and between the substrate 107 and the package substrate 102 on either side of a set of STPS interconnects 150. In particular, the differences in the material composition of a substrate 107 and a die 114 or a package substrate 102 may result in differential expansion and contraction due to heat generated during operation (as well as the heat applied during various manufacturing operations). To mitigate damage caused by this differential expansion and contraction (e.g., cracking, solder bridging, etc.), the DTS interconnects 140 and the STPS interconnects 150 may be formed larger and farther apart than DTD interconnects 130, which may experience less thermal stress due to the greater material similarity of the pair of dies 114 on either side of the DTD interconnects. In some embodiments, the DTS interconnects 140 disclosed herein may have a pitch between 25 microns and 250 microns. In some embodiments, the STPS interconnects 150 disclosed herein may have a pitch between 55 microns and 1000 microns, while the DTD interconnects 130 disclosed herein may have a pitch between 25 microns and 100 microns.
The microelectronic assembly 100 of FIG. 1 may also include a circuit board (not shown). The package substrate 102 may be coupled to the circuit board by second-level interconnects at the bottom face of the package substrate 102. The second-level interconnects may be any suitable second-level interconnects, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement or lands in a land grid array arrangement. The circuit board may be a motherboard, for example, and may have other components attached to it. The circuit board may include conductive pathways and other conductive contacts for routing power, ground, and signals through the circuit board, as known in the art. In some embodiments, the second-level interconnects may not couple the package substrate 102 to a circuit board, but may instead couple the package substrate 102 to another IC package, an interposer, or any other suitable component. In some embodiments, the substrate 107 may not be coupled to a package substrate 102, but may instead be coupled to a circuit board, such as a PCB.
Although FIG. 1 depicts a microelectronic assembly 100 having a substrate with a particular number of dies 114 and conductive pathways provided by the conductive material 108 coupled to other dies 114, this number and arrangement are simply illustrative, and a microelectronic assembly 100 may include any desired number and arrangement of dies 114. Although FIG. 1 shows the die 114-1 as a double-sided die and the dies 114-2, 114-3 as single-sided dies, the dies 114-2, 114-3 may be double-sided dies and the dies 114 may be a single-pitch die or a mixed-pitch die. In some embodiments, additional components may be disposed on the top face of the dies 114-2 and/or 114-3. In this context, a double-sided die refers to a die that has connections on both surfaces. In some embodiments, a double-sided die may include through TSVs to form connections on both surfaces. The active surface of a double-sided die, which is the surface containing one or more active devices and a majority of interconnects, may face either direction depending on the design and electrical requirements.
Many of the elements of the microelectronic assembly 100 of FIG. 1 are included in other ones of the accompanying drawings; the discussion of these elements is not repeated when discussing these drawings, and any of these elements may take any of the forms disclosed herein. Further, various elements are illustrated in FIG. 1 as included in the microelectronic assembly 100, but, in various embodiments, some of these elements may not be included. For example, in various embodiments, the further layers 111, the underfill material 127, and the package substrate 102 may not be present in the microelectronic assembly 100. In some embodiments, individual ones of the microelectronic assemblies 100 disclosed herein may serve as a system-in-package (SiP) in which multiple dies 114 having different functionality are included. In such embodiments, the microelectronic assembly 100 may be referred to as an SiP.
FIG. 2 is a schematic cross-sectional view of another example microelectronic assembly 100 according to some embodiments of the present disclosure. The configuration of the embodiment shown in the figure is like that of FIG. 1, except for differences as described further. Instead of including the glass core 110 as a part of the substrate 107, as was shown in FIG. 1, the microelectronic assembly 100 of FIG. 2 includes a glass core 110 on its own, where one or more dies 114 may be coupled to the glass core 110. In FIG. 2, the multi-layer die subassembly 104 includes the glass core 110 and the plurality of dies 114 as described above. The multi-layer die subassembly 104 may have a first surface 160-1 (e.g., the bottom face) and an opposing second surface 160-2 (e.g., the top face). The glass core 110 may provide mechanical stability to the multi-layer die subassembly 104 and/or the microelectronic assembly 100 of FIG. 2, may reduce warpage, and may provide a more robust surface for attachment of the multi-layer die subassembly 104 to a package substrate 102 or other substrate (e.g., an interposer or a circuit board).
The glass core 110 may include a cavity 129 with an opening facing the second surface 160-2 and the die 114-1 may be nested, fully or at least partially, in the cavity 129. As shown in FIG. 2, in cases where the die 114-1 is fully nested in a cavity 129, a top face of the die 114-1 may be planar with or below a top face of the glass core 110. In cases where the die 114-1 is partially nested in a cavity 129, a top face of the die 114-1 may extend above a top face of the glass core 110. The cavity 129 may be at least partially filled with a dielectric material 112A or 112B, described above. The die 114-1 may be attached to a bottom face of the cavity 129 by a die-attach film (DAF) 132. A DAF 132 may be any suitable material, including a non-conductive adhesive, die-attach film, a B-stage underfill, or a polymer film with adhesive property. A DAF 132 may have any suitable dimensions, for example, in some embodiments, a DAF 132 may have a thickness (e.g., height or z-height) between 5 microns and 10 microns.
The die 114-1 may be coupled to the dies 114-2, 114-3 in a layer above the die 114-1 through the DTD interconnects 130. The DTD interconnects 130 may be disposed between some of the conductive contacts 122 at the bottom of the dies 114-2, 114-3 and some of the conductive contacts 124 at the top of the die 114-1. Some other conductive contacts 122 at the bottom of the dies 114-2 and/or 114-3 may further couple one or more of the dies 114-2, 114-3 to the glass core 110 by glass core-to-die (GCTD) interconnects 142. The GCTD interconnects 142 may be disposed between some of the conductive contacts 122 at the bottom of the dies 114-2, 114-3 and some of the conductive contacts 128 at the top of the glass core 110. The GCTD interconnects 142 may be similar to the DTS interconnects 140, described above. In some embodiments, the underfill material 127 may extend between different ones of the dies 114 around the associated DTD interconnects 130 and/or GCTD interconnects 142. In some embodiments, a die 114-2 and/or a die 114-3 may be embedded in an insulating material 133. In some embodiments, an overall thickness (e.g., a z-height) of the insulating material 133 may be between 200 microns and 800 microns (e.g., substantially equal to a thickness of die 114-2 or 114-3 and the underfill material 127). In some embodiments, the insulating material 133 may form multiple layers (e.g., a dielectric material formed in multiple layers, as known in the art) and may embed one or more dies 114 in a layer. In some embodiments, the insulating material 133 may be a dielectric material, such as an organic dielectric material, a fire retardant grade 4 material (FR-4), BT resin, polyimide materials, glass reinforced epoxy matrix materials, or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In some embodiments, the insulating material 133 may be a mold material, such as an organic polymer with inorganic silica particles.
As shown in FIG. 2, the glass core 110 may further include conductive contacts 126 at the bottom of the glass core 110, and TGVs 115 may extend between and electrically couple conductive contacts 126 at the bottom of the glass core 110 and conductive contacts 128 at the top of the glass core 110. The conductive contacts 126, 128 may be similar to other conductive contacts disclosed herein (e.g., the conductive contacts 122, 124, 144, and/or 146), and may include bond pads, solder bumps, conductive posts, or any other suitable conductive contact, for example. As shown in FIG. 2, in some embodiments, at least some of the TGVs 115 may have an hourglass shape. For example, at least some of the TGVs 115 may has a first width at the first face of the glass core 110 (e.g., at the bottom face of the glass core 110), a second width at the second face of the glass core 110 (e.g., at the top face of the glass core 110), and a third width between the first face and the second face of the glass core 110, where the third width is smaller than the first width and the second width.
The dies 114-2, 114-3 may be electrically coupled to the package substrate 102 through the TGVs 115 and glass core-to-package substrate (GCTPS) interconnects 152, which may be power delivery interconnects or high-speed signal interconnects. The GCTPS interconnects 152 may be similar to the STPS interconnects 150, described above. The top face of the package substrate 102 may include a set of conductive contacts 146, the multi-layer die subassembly 104 may include a set of conductive contacts 126 on the first surface 160-1, and the GCTPS interconnects 152 may be between, and couple the conductive contacts 146 with corresponding ones of the conductive contacts 126. In some embodiments, the underfill material 127 may extend between the glass core 110 and the package substrate 102 around the associated GCTPS interconnects 152.
The glass core 110 included in a microelectronic assembly 100 as described with reference to FIG. 1 or FIG. 2 or included in any other microelectronic assembly or device, may be subject to edge stress and, therefore, susceptible to crack formation and propagation. For example, FIG. 3 illustrates singulation of a glass panel that may cause edge stress in glass cores. As shown in FIG. 3, during singulation process, a cutting tool 180 (e.g., a glass cutter, a diamond blade, or a saw) may be used to cut a glass panel 182 along some or all of saw streets 184 to separate the glass panel 182 into individual glass units 186 or into smaller blocks of two or more glass units 186. The saw streets 184 are referred to herein as “saw streets” although they may also be referred to as “scribe lines,” “saw lines,” or “singulation lines/streets.”
After singulation, any of the glass units 186 may serve as a glass core 110. However, as a result of cutting, the surfaces of the glass units 186 along the saw streets 184 (i.e., at least some edges of the glass units 186) may be subject to edge stress and, as a result, may have cracks or fractures, have high surface roughness or jagged edges, or may be otherwise uneven. One or more edge features as described herein may be implemented in the glass panel 182 during or after the singulation process so that crack formation and/or propagation in a glass core 110 formed by one of the singulated glass unit 186 may be reduced. FIGS. 4A-4B illustrate approximate locations of edge features in a glass core 110, according to some embodiments of the present disclosure. In particular, FIG. 4A illustrates a cross-sectional side view of a glass core 110, while FIG. 4B illustrates a top-down view of a glass core 110 (not to scale with the glass core 110 shown in FIG. 4A). As shown in FIG. 4A, a glass core 110 may include a first face 190-1 and an opposing second face 190-2, which may, e.g., be bottom and top surfaces of the glass core 110 when the glass core 110 is included in a microelectronic assembly 100. When TGVs are formed in the glass core 110, e.g., the TGVs 115 described above, openings 192 may first be formed in the glass core 110, extending between the first face 190-1 and the second face 190-2, where the openings 192 may then be filled with one or more conductive materials, such as copper. FIG. 4A also illustrates opposite edges 194-1 and 194-2, and FIG. 4B further illustrates the other pair of opposite edges 194-3 and 194-4 (the four edges 194-1, 194-2, 194-3, and 194-4 collectively referred to herein as “edges 194”), where the edges 194 are surfaces of the glass core 110 that extend between the first face 190-1 and the second face 190-2. FIG. 4A further illustrates edge regions 196-1 and 196-2 (collectively referred to herein as “edge regions 196”), where one or more edge features as described herein may be implemented. As shown in FIG. 4A, the edge region 196-1 is a region including the edge 194-1 and extending from the edge 194-1 into the glass core 110 (i.e., extending towards the opposite edge 194-2) by a certain depth 198-1, while the edge region 196-2 is a region including the edge 194-2 and extending from the edge 194-2 into the glass core 110 (i.e., extending towards the opposite edge 194-1) by a certain depth 198-2. In various embodiments, the depths 198-1, 198-2 may be less than about 10% (e.g., less than about 7% or less than about 5%) of the total width 199 (e.g., a dimension of the glass core 110 measured in the same direction as the depths 198-1, 198-2) of the glass core 110. FIG. 4B illustrates that a single edge region 196 may be defined as a closed contour that follows each of the edges 194 of the glass core 110 and extends from the edges 194 of the glass core 110 by a certain depth 198 (the depth 198 measured in a direction perpendicular to the respective edges 194). Such a single edge region 196 may be similar to a ring around an active area 197 of the glass core 110, except that the footprint (e.g., top-down) shape of it is not circular as in a ring, but rectangular. The active area 197 may be an area where TGVs 115 are implemented, and/or an area within which other components are coupled to the glass core 110. In general, the edge region 196 only occupies a portion of the total area of a face 190 of the glass core 110, e.g., less than about 20% (e.g., less than about 10% or less than about 5%) of the total area of a face 190 of the glass core 110. FIG. 4B illustrates the edge region 196 that has four portions along the four edges 194, where all portions have the same depth 198, but this may be different in other embodiments in that the edge region 196 along different edges 194 may have different depths 198.
One or more edge features as described herein may be implemented in any one or more of the edge regions 196. At a high level, edge features described herein may be categorized as edge features based on providing a layer of a material described as an “edge protection coating” (e.g., edge features illustrated in FIGS. 5-7), edge features based on edge shape control (e.g., edge features illustrated in FIGS. 8-18), edge features based on providing a frame protection (e.g., edge features illustrated in FIG. 19), and edge features based on glass edge treatment after singulation (e.g., edge features illustrated in FIGS. 20-23). Edge features based on glass edge treatment after singulation may further be categorized as edge features based on thermal treatment (e.g., edge features illustrated in FIGS. 20-22) and edge features based on chemical treatment (e.g., edge features illustrated in FIG. 24). Edge features based on thermal treatment may be categorized even further as edge features based on heating and rapidly cooling the glass edge (e.g., edge features illustrated in FIG. 20), edge features based on laser peening (e.g., edge features illustrated in FIG. 21), and edge features based on ultrafast lasers (e.g., edge features illustrated in FIG. 22). In some embodiments, each of the edge features described herein may be implemented in a glass core 110 as a stand-alone edge feature to help mitigate or reduce crack formation and/or propagation. In other embodiments, two or more different edge features described herein, in any combination, may be implemented for a glass core 110. Details of various techniques will now be described. It should be noted that, although some drawings illustrating various embodiments of edge features show glass cores 110 (e.g., FIGS. 6A-6C), it is to be understood that the same features may be applied to a glass panel 182 or a structure that is smaller than a glass panel 182 but larger than a glass core 110, e.g., to a structure that includes a plurality of the individual glass units 186 (e.g., half of the glass panel 182 or quarter of the glass panel 182). Although FIGS. 5-23 do not show TGVs 115 in any of the glass cores 110 and do not show other components that may be coupled to the glass cores 110, this is only in order to not clutter the drawings, and, in general, the glass cores 110 shown in any of FIGS. 5-23 may be the glass cores 110 as described with reference to, e.g., FIG. 1 or FIG. 2.
FIG. 5 is a schematic side, cross-sectional view of one example microelectronic assembly 100 with an edge protection coating 202, according to some embodiments of the present disclosure. The microelectronic assembly 100 of FIG. 5 illustrates a multi-layer glass substrate that includes the glass core 110 and the dielectric material 112 of the substrate 107, as described with reference to FIG. 1. In this setting, FIG. 5 illustrates how an edge protection coating 202 may be applied around the edges of the multi-layer glass substrate of the microelectronic assembly 100. In various embodiments, the edge protection coating 202 may be provided on all edges of the multi-layer glass substrate, or only on some but not all of the edges of the multi-layer glass substrate. As shown in FIG. 5, the edge protection coating 202 may include a portion on the edge of the glass core 110, a portion on the edge of the dielectric material 112, and a portion on the edge of the further layers 111 that may be present below the glass core 110, all of which portions could be materially continuous with one another. Providing the protective coating 202 on the edges may help mitigate or reduce crack formation and/or propagation in the glass core 110. In some embodiments, the edge protection coating 202 may further include a portion on top of the dielectric material 112 (e.g., on top of the dielectric material 112B, as shown in FIG. 5), and a portion on the bottom of the further layers 111 (as also shown in FIG. 5). Such portions may function as a dam to improve the handleability of the glass core 110 in the downstream processes. In general, the edge protection coating 202 may include a material having one or more of the following characteristics: 1) be in-situ ultraviolet (UV) curable, 2) have good mechanical properties (e.g., have tensile strengths above about 100 megapascal (MPa), 3) have a pot-life of several weeks, and 4) be easy to apply on the edges of the microelectronic assembly 100 without compromising the active components in areas within the edges. In some embodiments, the edge protection coating 202 may be applied using an inkjet coating process. In various embodiments, a thickness of the edge protection coating 202 may be between about 1 nanometer and 100 micron, e.g., between about 10 nanometers and 50 micron, or between about 50 nanometers and 1 micron.
In some embodiments, the edge protection coating 202 may include a solder resist, e.g., a polymer material that is resistant to the heat of soldering. In some embodiments, the edge protection coating 202 may include a dielectric material, e.g., a photo-imageable dielectric (i.e., a dielectric material that can be patterned using a photolithography process). In some embodiments, the edge protection coating 202 may be a material having a relatively low Young's modulus, e.g., between about 1 gigapascal (GPa) and 10 GPa, where the Young's modulus may be defined as the ratio of stress to strain in a material undergoing deformation. Such embodiments may help dissipate stress better. In some embodiments, the edge protection coating 202 may be a material having a glass transition temperature between about 150 and 300 degrees Celsius, e.g., between about 200 and 260 degrees Celsius. In some embodiments, the edge protection coating 202 may be a material having a tensile strength of between about 100 MPa, e.g., of about 180 MPa.
In some embodiments, the edge protection coating 202 may be a material having a relatively low CTE. CTE is a measure of how a material expands or contracts with changes in temperature and is typically defined as the fractional increase in length per unit rise in temperature, measured in, e.g., parts per million (ppm) per degrees Kelvin (K) or ppm/K. Materials that may be used for glass cores and metals (e.g., metals filling TGVs in glass cores) have significantly different CTEs. Metals have relatively high CTEs, meaning that they may expand and contract significantly with changes in temperature. Glass, on the other hand, has a much lower CTE and is less responsive to temperature changes. For example, a CTE of glass may be on the order of about 3.5 ppm/K, while a CTE of a metal such as copper may be on the order of about 15 ppm/K. When a metal is in close contact with glass (e.g., a metal within a TGV in the glass core), and the assembly is exposed to temperature variations such as heating or cooling, the metal will heat up or cool down much faster, and to a greater extent, than the glass. This leads to the generation of significant thermal stress at the interface between the two materials. The high thermal stress can exceed the strength of the glass, leading to the formation of cracks, which may then propagate and compromise the structural integrity of the glass. Even if cracks don't form immediately, the repeated thermal cycling can gradually weaken the glass surface, potentially leading to the development of surface flaws or micro-cracks. Prolonged exposure to CTE mismatch-induced stresses can cause gradual degradation of the glass, making it more prone to failure over time. Including the edge protection coating 202 as a material having a CTE lower than that of metals using in other portions of the glass core 110 (e.g., in the TGVs 115, shown in FIG. 5) and/or in the conductive traces 108A or conductive vias 108B may help reduce issues associated with the CTE mismatch-induced stresses. In some embodiments, the edge protection coating 202 may be a material having a CTE below about 15 ppm/K, e.g., below about 10 ppm/K or below about 7 ppm/K. In other embodiments, the edge protection coating 202 may have a CTE above 15 ppm/K.
FIGS. 6A-6C provide cross-sectional side views of glass cores 110 illustrating variations in the extent of edge protection coatings, according to some embodiments of the present disclosure. In particular, FIG. 6A illustrates an embodiment where an edge protection coating 212 provided only on a portion of an edge 194 of the glass core 110 (e.g., on the edge 194-1 or the edge 194-2, as shown in FIG. 6A, but not along the entire length of the edge 194). FIG. 6B illustrates an embodiment where the edge protection coating 212 is provided along the entire length of the edge 194 but not on the edges of build-up layers 210 that may be provided on top of the glass core 110 (e.g., over the face 190-2) and on the bottom of the glass core 110 (e.g., below the face 190-1). The build-up layer 210 provided on top of the glass core 110 may be implemented as the dielectric material 112 with conductive pathways of the conductive material 108, described above. The build-up layer 210 provided on the bottom of the glass core 110 may be implemented as the further layers 111 with conductive pathways of the conductive material 108 described above. In some embodiments, only the build-up layer 210 on top or on the bottom of the glass core 110 may be present, but not both. FIG. 6C illustrates an embodiment where the edge protection coating 212 is provided along the entire length of the edge 194 and at least on a portion, or on the entire length, of the edges of the build-up layers 210 on top and/or on the bottom of the glass core 110.
In some embodiments, the edge protection coating 212 may include any of the materials described with reference to the edge protection coating 202. In other embodiments, the edge protection coating 212 may include a material that could generate compressive stress along the edges 194 of the glass core 110, so that formation or propagation of cracks originating at the edges 194 under the CTE-mismatch driven tensile stress may be reduced or eliminated. In some such embodiments, the edge protection coating 212 may include a thin film of metal, alloy, ceramic, or polymer material along the edges 194 of the glass core 110. For example, the edge protection coating 212 may include one or more of molybdenum, chromium, silicon dioxide, silicon nitride, silicon carbide, or aluminum nitride. In general, the edge protection coating 212 may include any material that can generate a relatively large (e.g., on the order of 100-1000 MPa) compressive residual stress along the glass core edge surfaces. For example, materials having a CTE lower than that of the glass core 110 may be used, as they may advantageously create compressive stress within the glass core 110 and tensile stress in the layer of the edge protection coating 212. In some embodiments, a thickness of the edge protection coating 212 may be below about 500 micron. In various embodiments, the edge protection coating 212 may be provided on all edges 194 of the glass core 110, or only on some but not all of the edges 194. In various embodiments, the edge protection coating 212 may be provided using deposition techniques such as cold spray, thermal spray, vapor deposition (e.g., chemical vapor deposition (CVD) or physical vapor deposition (PVD)), or electroplating.
In some embodiments, the edge protection coatings 202 or 212 may include crack-healing materials. FIGS. 7A-7C illustrate a process of healing cracks using an edge protection coating 222 with a crack-healing material, according to some embodiments of the present disclosure. In order to not clutter the drawings, the build-up layers shown in FIG. 5 or FIGS. 6A-6C are not shown in FIGS. 7A-7C, but the edge protection coating 222 may be arranged according to any geometric considerations described with reference to the edge protection coating 202 of FIG. 5 or the edge protection coating 212 of FIGS. 6A-6C.
As used herein, “crack-healing” refers to the ability of a material to at least partially repair the cracks in the glass core 110 autonomously and at least partially maintain the structural integrity of the glass core 110. To that end, nanomaterials and nanostructures in polymers provide large surface area, rich functional groups, and unique properties that may facilitate the healing process in glass. As shown in FIG. 7A, an edge protection coating 222 may include a matrix 224 in which crack-healing particles 226 may be dispersed. The matrix 224 may include any suitable polymer, such as epoxy. In some embodiments, the matrix 224 may include a thermoset, i.e., a type of polymer that, once formed, undergoes a chemical reaction that irreversibly solidifies or “sets” the material. In some embodiments, such a process may be induced by heat, catalysts, or a combination of both. A thermoset may include one or more polymer materials such as phenolics, alkyds, vinyl esters, unsaturated polyesters, polyurethanes, or aminoplastics. The crack-healing particles 226 may include any suitable nanomaterials or nanostructures, e.g., microcapsules or nanocapsules, filled with a healing agent. The healing agent may include materials such as poly (urea-formaldehyde) (PUF), polyurethane, poly (melamine-urea-formaldehyde) (PMUF), or poly (melamine-formaldehyde) (PMF). The polymerization and/or crosslinking of the healing agent, possibly in presence of the catalyst, may mend the cracked area and arrest further growth of the crack. In some embodiments, the crack-healing particles 226 may include a shell filled with a healing agent. The shell may be a ceramic shell. For example, the shell may include silicon dioxide or any other non-metallic inorganic compounds. Ceramics, including silicon oxide-based materials, are known for their hardness, high melting points, electrical insulating properties, and resistance to corrosion, making them a good choice for the shells of the crack-healing particles 226. The healing agent may include an uncured organic monomer or oligomer. When a crack-healing particle 226 is broken/cracked, e.g., through mechanical means such as from the impact/stress on the edges 194 of the glass core 110, the healing agent will flow out of the particle and toward any flaws or defects in the glass core 110, possibly expanding (e.g., upon application of heat), filling the defects in the glass core 110. The healing agent may then be cure, restoring the strength of the glass core 110. FIG. 7A illustrates a glass core 110 with the edge protection coating 222 with the matrix 224 and the crack-healing particles 226 before cracks are formed. FIG. 7B illustrates the same glass core 110 as in FIG. 7A but after cracks 223 are formed at the edges 194. FIG. 7C illustrates the glass core 110 of FIG. 7B after the healing agent of the crack-healing particles 226 at least partially filled the cracks 223. FIG. 7C illustrates less of the crack-healing particles 226 than FIG. 7B to represent that some of the crack-healing particles 226 are broken to release their healing agents.
If used, catalysts may include materials such as Hoveyda-Grubbs catalysts. In some embodiments, catalysts may include ruthenium. In some embodiments, catalysts may be dispersed in the glass core 110 and not in the edge protection coating 222. Upon crack growth, the microcapsules or nanocapsules of the crack-healing particles 226 may be ruptured and may release the healing agent into the crack in the glass core 110. The healing agent would then contact the catalyst dispersed in the glass core 110, which would initiate polymerization/crosslinking of the healing agent, thereby filling the crack. In other embodiments, catalysts may be coated on the edges 194 of the glass core 110. In still other embodiments, catalysts may be coated on the outer shell of the crack-healing particles 226. In all of these embodiments, upon crack growth, the microcapsules or nanocapsules of the crack-healing particles 226 may be ruptured and the healing agent would contact the catalyst, which would initiate polymerization/crosslinking of the healing agent and at least partially fill the crack. Breaking a polymer may involve the rupture of chemical and physical bonds, and the reformation of these bonds results in crack-healing. Crack-healing through chemical approaches may utilize dynamic covalent bonds from reactions such as Diels-Alder reaction and disulfide bond formation, while crack-healing through physical approaches may utilize intermolecular interactions like hydrogen bonds. Incorporating nanomaterials in crack-healing systems may advantageously provide large interfacial surface area, enhanced electrical and mechanical properties, improved response to external stimuli, and increased conversion efficiency of electromagnetic energy to heat.
Edge features based on edge shape control are illustrated in FIGS. 8-12. Such edge features are based on recognition that stress within the glass core 110 and, therefore, the likelihood of crack formation and propagation, depends on the edge shapes of the glass core 110 itself, as well as the edge shapes of the build-up layers 210 and of the edge protection coatings (e.g., any one of the edge protection coatings 202, 212, 222, described above).
FIGS. 8A-8C provide cross-sectional side views illustrating variations in edge shapes of glass cores 110, according to some embodiments of the present disclosure. For the purposes of discussion, it may be assumed that FIGS. 8A-8C, as well as FIGS. 11A-11H, and FIGS. 12-18 illustrate only the details of the edge 194-2 of the glass cores 110 as described herein, and the glass cores 110 shown in these drawings may extend further to the left than what is shown in the drawings. For example, it may be assumed that FIGS. 8A-8C, FIGS. 11A-11H, and FIGS. 12-18 illustrate only the edge region 196-2 portion of the glass cores 110. Descriptions provided for these drawings are applicable to other edges 194 of the glass core 110.
FIG. 8A illustrates an embodiment where an edge 194-2 may be straight and substantially perpendicular to the faces 190-1 and 190-2. Such an embodiment may be advantageous in terms of relatively easy manufacturing. In some embodiments, the straight edge 194-2 as shown in FIG. 8A may be realized using blade cutting. For example, mechanical blade dicing process may be used to cut the glass panel 182 into individual glass units 186 with straight edges 194, during which abrasive particles on a blade make contact with the workpiece to achieve a cut. In some embodiments, the straight edge 194-2 as shown in FIG. 8A may be realized using laser cutting and breaking. For example, a Bessel beam or a filamentation laser can used to induce a curtain of defects in the glass. The glass is mechanically separated around these regions, leaving a straight glass edge. Filamentation is a glass cutting technique that may use a high-energy laser to create a self-focusing phenomenon inside the glass. Bessel beam is based on creating a laser interference pattern inside the glass. Laser cutting may result in an edge 194 of a glass core 110 protruding from the edges of the build-up layers 210, e.g., as shown in FIG. 11B or FIG. 11D.
FIG. 8B illustrates an embodiment where an edge 194-2 may be chamfered in that it may include portions that are beveled or angled at an angle other than 90 degrees with respect to the faces 190-1 and 190-2. Such an embodiment may be advantageous in terms of reducing stress concentration zones in the glass core 110, compared to a straight edge 194-2, and, thereby, reducing the susceptibility of the glass core 110 to crack formation and propagation. FIG. 8C illustrates an embodiment where an edge 194-2 may be rounded. Similar to FIG. 8B, such an embodiment may be advantageous in terms of reducing stress concentration zones in the glass core 110, compared to a straight edge 194-2, although it may be more difficult to manufacture than the chamfered edge as shown in FIG. 8B. In some embodiments, the chamfered and rounded edges 194-2 as shown in FIG. 8B and FIG. 8C may be realized using a mechanical grinding and polishing process, where either a tool specifically curated for each shape is used, or where the polishing pad is moved relative to the workpiece to achieve the desired edge shape. In other embodiments, the chamfered and rounded edges 194-2 as shown in FIG. 8B and FIG. 8C may be realized using laser techniques. For example, an ablation process may be used to achieve a specific edge profile by carefully selecting the ablation pattern, depth, and shadowing effects. In this process, atoms may be ejected from the glass through rapid heat transfer. In yet other embodiments, the chamfered and rounded edges 194-2 as shown in FIG. 8B and FIG. 8C may be realized using a combination of a laser and chemical etching. In some embodiments, this process may be used at the beginning of the line, where trenches with a specific geometry are created through a laser perforation process, followed by chemical etching. The laser perforation process may be similar to the Bessel beam process described above. Chemical etching using agents such as sodium hydroxide (NaOH) may be used to form the trenches. Besides the chamfered and rounded edges 194-2 as shown in FIG. 8B and FIG. 8C, the edges 194 of the glass core 110 may have other shapes that are different from the 90 degrees as shown in FIG. 8A or from having sharp (i.e., less than 90 degrees) corners, which may reduce stress concentration zones and, thereby, reduce the susceptibility of the glass core 110 to crack formation and propagation.
FIGS. 9A-9B provide cross-sectional side views illustrating variations in edge shapes of edges 214 of the build-up layers 210, according to some embodiments of the present disclosure. For the purposes of discussion, it may be assumed that FIGS. 9A-9B, as well as FIGS. 11A-11H, and FIGS. 12-18 illustrate only the details of the edge 214 on the right side of the build-up layer 210 as described herein, and the build-up layers 210 shown in these drawings may extend further to the left than what is shown in the drawings. For example, it may be assumed that FIGS. 9A-9B, FIGS. 11A-11H, and FIGS. 12-18 illustrate only the edge region 196-2 portion of the glass cores 110 with the build-up layers 210. Descriptions provided for these drawings are applicable to other edges 214 of the build-up layers 210.
FIG. 9A illustrates an embodiment where an edge 214 may be straight and substantially perpendicular to the faces 190-1 and 190-2 of the glass core 110 on which the build-up layer 210 is provided. Such an embodiment may be advantageous in terms of relatively easy manufacturing. In some embodiments, the straight edge 214 as shown in FIG. 9A may be realized using blade cutting (mechanical blade dicing). In some embodiments, mechanical blade dicing may be used to fully cut through the build-up layer 210 and the glass core 110, e.g., to realize an edge profile as shown in FIG. 11A. In other embodiments, mechanical blade dicing may be used to cut through the build-up layer 210 but not through the glass core 110, e.g., to realize an edge profile as shown in FIG. 11B, FIG. 11C, or FIG. 11G.
FIG. 9B illustrates an embodiment where an edge 214 may be chamfered in that it may include portions that are beveled or angled at an angle other than 90 degrees with respect to the faces 190-1 and 190-2 of the glass core 110 on which the build-up layer 210 is provided. Such an embodiment may be advantageous in terms of reducing stress concentration zones in the glass core 110, compared to a straight edge 214, and, thereby, reducing the susceptibility of the glass core 110 to crack formation and propagation. In some embodiments, the chamfered edge 214 as shown in FIG. 9B may be realized using partial blade dicing where mechanical blade dicing is used to cut the build-up layer 210 at different angles from different faces. In some embodiments, the chamfered edge 214 as shown in FIG. 9B may be realized using laser techniques such as laser ablation, similar to that described above with reference to FIG. 8B and FIG. 8C, where a specific edge profile of the build-up layer 210 may be achieved by carefully selecting the ablation pattern, depth, and shadowing effects. In this process, atoms may be ejected from the layers of polymer/dielectric materials of the build-up layer 210 through rapid heat transfer.
FIGS. 10A-10C provide cross-sectional side views illustrating variations in edge shapes of edges 234 of the edge protection coatings 232, according to some embodiments of the present disclosure. Similar to FIGS. 8 and 9, for the purposes of discussion, it may be assumed that FIGS. 10A-10C, as well as FIGS. 12-18 illustrate only the details of the edge 234 on the right side of the edge protection coating 232 as described herein, and the edge protection coatings 232 shown in these drawings may extend further to the left than what is shown in the drawings. For example, it may be assumed that FIGS. 10A-10C and FIGS. 12-18 illustrate only the edge region 196-2 portion of the glass cores 110 with the build-up layers 210 and the edge protection coatings 232. Descriptions provided for these drawings are applicable to other edges 234 of the edge protection coatings 232. The edge protection coating 232 may be any one of the edge protective coatings 202, 212, 222, described above.
FIG. 10A illustrates an embodiment where an edge 234 may be straight and substantially perpendicular to the faces 190-1 and 190-2 of the glass core 110. Such an embodiment may be advantageous in terms of relatively easy manufacturing. In some embodiments, the straight edge 234 as shown in FIG. 10A may be realized using blade dicing of edge molded or coated edge protection coatings 232. In other embodiments, the straight edge 234 as shown in FIG. 10A may be realized using laser dicing of edge molded edge protection coatings 232.
FIG. 10B illustrates an embodiment where an edge 234 may be chamfered in that it may include portions that are beveled or angled at an angle other than 90 degrees with respect to the faces 190-1 and 190-2. Such an embodiment may be advantageous in terms of reducing stress concentration zones in the glass core 110, compared to a straight edge 234, and, thereby, reducing the susceptibility of the glass core 110 to crack formation and propagation. In some embodiments, the chamfered edge 234 as shown in FIG. 10B may be realized using mechanical edge grinding. In other embodiments, the chamfered edge 234 as shown in FIG. 10B may be realized using laser ablation of the edge protection coating 232, followed by lase cutting.
FIG. 10C illustrates an embodiment where an edge 234 may be rounded or dome-shaped. Similar to the embodiment of FIG. 10B, such an embodiment may be advantageous in terms of reducing stress concentration zones in the glass core 110, compared to a straight edge 234, and, thereby, reducing the susceptibility of the glass core 110 to crack formation and propagation. In some embodiments, the rounded or dome-shaped edge 234 as shown in FIG. 10C may be realized using roller coating and may be attributed to the surface tension of the material of the edge protection coating 232.
FIGS. 11A-11H provide cross-sectional side views illustrating portions of the microelectronic assemblies 100 with variations in combinations of glass cores 110 and build-up layers 210 with different edge shapes, according to some embodiments of the present disclosure. FIG. 11A illustrates a conventional arrangement where both the glass core 110 and the build-up layers 210 have substantially straight edges, aligned with one another. The shapes shown in FIGS. 11B-11H may be particularly beneficial in reducing stress concentration zones in the glass core 110, compared to the embodiment shown in FIG. 11A, and, thereby, reducing the susceptibility of the glass core 110 to crack formation and propagation. In various embodiments of FIGS. 11A-11H where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210, the distance of the protrusion may be similar to the depth 198, described above.
FIG. 11B illustrates a glass core 110 with the edge 194-2 being a straight edge (e.g., as shown in FIG. 8A) and build-up layer 210 with the edges 214 being straight edges (e.g., as shown in FIG. 9A), where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210. FIG. 11C illustrates a glass core 110 with the edge 194-2 being a chamfered edge (e.g., as shown in FIG. 8B) and build-up layer 210 with the edges 214 being straight edges (e.g., as shown in FIG. 9A), where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210. FIG. 11D illustrates a glass core 110 with the edge 194-2 being a straight edge (e.g., as shown in FIG. 8A) and build-up layer 210 with the edges 214 being chamfered edges (e.g., as shown in FIG. 9B), where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210. FIG. 11E illustrates a glass core 110 with the edge 194-2 being a rounded edge (e.g., as shown in FIG. 8C) and build-up layer 210 with the edges 214 being chamfered edges (e.g., as shown in FIG. 9B), where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210. FIG. 11F illustrates a glass core 110 with the edge 194-2 being a chamfered edge (e.g., as shown in FIG. 8B) and build-up layer 210 with the edges 214 being chamfered edges (e.g., as shown in FIG. 9B), where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210. FIG. 11G illustrates a glass core 110 with the edge 194-2 being a rounded edge (e.g., as shown in FIG. 8C) and build-up layer 210 with the edges 214 being straight edges (e.g., as shown in FIG. 9A), where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210. FIG. 11H illustrates a glass core 110 with the edge 194-2 being a straight edge (e.g., as shown in FIG. 8A) and build-up layer 210 with the edges 214 being chamfered edges (e.g., as shown in FIG. 9B), similar to FIG. 11D, but where the glass core 110 does not protrude beyond (e.g., is aligned with) the edge 214 of the build-up layers 210.
FIGS. 12-18 provide cross-sectional side views illustrating portions of the microelectronic assemblies 100 with variations in combinations of glass cores 110, build-up layers 210, and edge protection coatings 232 with different edge shapes, according to some embodiments of the present disclosure. The shapes shown in FIGS. 12-18 may be particularly beneficial in reducing stress concentration zones in the glass core 110, and, thereby, reducing the susceptibility of the glass core 110 to crack formation and propagation. In various embodiments of FIGS. 12-18 where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210, the distance of the protrusion may be similar to the depth 198, described above. In FIGS. 12-18, a differentiation is made between edge protection coatings 232 that are partial coatings and edge protection coatings 232 that are partial coatings. As used herein, an edge protection coating may be described as partial if it does not extend along the entire length of the edge with the glass core 110 and the build-up layers 210. For example, the edge protection coatings 212 shown in FIG. 6A and FIG. 6B are partial coatings, while the edge protection coating 212 shown in FIG. 6C is a full coating.
FIGS. 12A-12G provide cross-sectional side views illustrating portions of the microelectronic assemblies (e.g., the microelectronic assemblies 100) with variations in combinations of glass cores 110, build-up layers 210, and edge protection coatings 232 with different edge shapes where the edge protection coatings 232 are partial chamfered coatings, according to some embodiments of the present disclosure. FIG. 12A illustrates a glass core 110 with the edge 194-2 being a straight edge (e.g., as shown in FIG. 8A), build-up layers 210 with the edges 214 being straight edges (e.g., as shown in FIG. 9A), where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210, and further illustrating an edge protection coating 232 with the edge 234 being a chamfered edge (e.g., as shown in FIG. 10B). FIG. 12B illustrates a glass core 110 with the edge 194-2 being a straight edge (e.g., as shown in FIG. 8A), build-up layers 210 with the edges 214 being straight edges (e.g., as shown in FIG. 9A), and further illustrating an edge protection coating 232 with the edge 234 being a chamfered edge (e.g., as shown in FIG. 10B), similar to FIG. 12A, but where the glass core 110 does not protrude beyond (e.g., is aligned with) the edge 214 of the build-up layers 210. FIG. 12C illustrates a glass core 110 with the edge 194-2 being a chamfered edge (e.g., as shown in FIG. 8B), build-up layers 210 with the edges 214 being straight edges (e.g., as shown in FIG. 9A), where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210, and further illustrating an edge protection coating 232 with the edge 234 being a chamfered edge (e.g., as shown in FIG. 10B). FIG. 12D illustrates a glass core 110 with the edge 194-2 being a straight edge (e.g., as shown in FIG. 8A), build-up layers 210 with the edges 214 being chamfered edges (e.g., as shown in FIG. 9B), where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210, and further illustrating an edge protection coating 232 with the edge 234 being a chamfered edge (e.g., as shown in FIG. 10B). FIG. 12E illustrates a glass core 110 with the edge 194-2 being a rounded edge (e.g., as shown in FIG. 8C), build-up layers 210 with the edges 214 being chamfered edges (e.g., as shown in FIG. 9B), where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210, and further illustrating an edge protection coating 232 with the edge 234 being a chamfered edge (e.g., as shown in FIG. 10B). FIG. 12F illustrates a glass core 110 with the edge 194-2 being a rounded edge (e.g., as shown in FIG. 8C), build-up layers 210 with the edges 214 being straight edges (e.g., as shown in FIG. 9A), where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210, and further illustrating an edge protection coating 232 with the edge 234 being a chamfered edge (e.g., as shown in FIG. 10B). FIG. 12G illustrates a glass core 110 with the edge 194-2 being a chamfered edge (e.g., as shown in FIG. 8B), build-up layers 210 with the edges 214 being chamfered edges (e.g., as shown in FIG. 9B), where the glass core 110 protrudes beyond the edge 214 of the build-up layers 210, and further illustrating an edge protection coating 232 with the edge 234 being a chamfered edge (e.g., as shown in FIG. 10B)
FIGS. 13A-13H provide cross-sectional side views illustrating portions of the microelectronic assemblies (e.g., the microelectronic assemblies 100) with variations in combinations of glass cores 110, build-up layers 210, and edge protection coatings 232 with different edge shapes where the edge protection coatings 232 are rounded edge coatings, according to some embodiments of the present disclosure. FIG. 13A provides an illustration similar to that of FIG. 12A, except where the edge 234 shown in FIG. 13A is a rounded edge (e.g., as shown in FIG. 10C). FIG. 13B provides an illustration similar to that of FIG. 12B, except where the edge 234 shown in FIG. 13B is a rounded edge. FIG. 13C provides an illustration similar to that of FIG. 12C, except where the edge 234 shown in FIG. 13C is a rounded edge. FIG. 13D provides an illustration similar to that of FIG. 12D, except where the edge 234 shown in FIG. 13D is a rounded edge. FIG. 13E provides an illustration similar to that of FIG. 12E, except where the edge 234 shown in FIG. 13E is a rounded edge. FIG. 13F provides an illustration similar to that of FIG. 12F, except where the edge 234 shown in FIG. 13F is a rounded edge. FIG. 13G provides an illustration similar to that of FIG. 12G, except where the edge 234 shown in FIG. 13G is a rounded edge. FIG. 13H illustrates a glass core 110 with the edge 194-2 being a straight edge (e.g., as shown in FIG. 8A), build-up layers 210 with the edges 214 being chamfered edges (e.g., as shown in FIG. 9B), and further illustrating an edge protection coating 232 with the edge 234 being a rounded edge, similar to FIG. 13D, but where the glass core 110 does not protrude beyond (e.g., is aligned with) the edge 214 of the build-up layers 210.
FIGS. 14A-14H provide cross-sectional side views illustrating portions of the microelectronic assemblies (e.g., the microelectronic assemblies 100) with variations in combinations of glass cores 110, build-up layers 210, and edge protection coatings 232 with different edge shapes where the edge protection coatings 232 are thin-film coatings (e.g., coatings having a thickness less than about 100 micron, e.g., less than about 50 micron or less than about 25 micron), according to some embodiments of the present disclosure. FIG. 14A provides an illustration similar to that of FIG. 13A, except where the edge protection coating 232 shown in FIG. 14A is a thin-film coating. FIG. 14B provides an illustration similar to that of FIG. 13B, except where the edge protection coating 232 shown in FIG. 14B is a thin-film coating. FIG. 14C provides an illustration similar to that of FIG. 13C, except where the edge protection coating 232 shown in FIG. 14C is a thin-film coating. FIG. 14D provides an illustration similar to that of FIG. 13D, except where the edge protection coating 232 shown in FIG. 14D is a thin-film coating. FIG. 14E provides an illustration similar to that of FIG. 13E, except where the edge protection coating 232 shown in FIG. 14E is a thin-film coating. FIG. 14F provides an illustration similar to that of FIG. 13F, except where the edge protection coating 232 shown in FIG. 14F is a thin-film coating. FIG. 14G provides an illustration similar to that of FIG. 13G, except where the edge protection coating 232 shown in FIG. 14G is a thin-film coating. FIG. 14H provides an illustration similar to that of FIG. 13H, except where the edge protection coating 232 shown in FIG. 14H is a thin-film coating.
FIGS. 15A-15H provide cross-sectional side views illustrating portions of the microelectronic assemblies (e.g., the microelectronic assemblies 100) with variations in combinations of glass cores 110, build-up layers 210, and edge protection coatings 232 with different edge shapes where the edge protection coatings 232 are partial rounded coatings, according to some embodiments of the present disclosure. FIGS. 15A-15H are similar to FIGS. 13A-13H, except that the edge protection coatings 232 shown in FIGS. 13A-13H are full coatings and the edge protection coatings 232 shown in FIGS. 15A-15H are partial coatings. FIG. 15A provides an illustration similar to that of FIG. 13A, except where the edge protection coating 232 shown in FIG. 15A is a partial coating. FIG. 15B provides an illustration similar to that of FIG. 13B, except where the edge protection coating 232 shown in FIG. 15B is a partial coating. FIG. 15C provides an illustration similar to that of FIG. 13C, except where the edge protection coating 232 shown in FIG. 15C is a partial coating. FIG. 15D provides an illustration similar to that of FIG. 13D, except where the edge protection coating 232 shown in FIG. 15D is a partial coating. FIG. 15E provides an illustration similar to that of FIG. 13E, except where the edge protection coating 232 shown in FIG. 15E is a partial coating. FIG. 15F provides an illustration similar to that of FIG. 13F, except where the edge protection coating 232 shown in FIG. 15F is a partial coating. FIG. 15G provides an illustration similar to that of FIG. 13G, except where the edge protection coating 232 shown in FIG. 15G is a partial coating. FIG. 15H provides an illustration similar to that of FIG. 13H, except where the edge protection coating 232 shown in FIG. 15G is a partial coating.
FIGS. 16A-16H provide cross-sectional side views illustrating portions of the microelectronic assemblies (e.g., the microelectronic assemblies 100) with variations in combinations of glass cores 110, build-up layers 210, and edge protection coatings 232 with different edge shapes where the edge protection coatings 232 are straight edge full coatings, according to some embodiments of the present disclosure. FIGS. 16A-16H are similar to FIGS. 13A-13H, except that the edge protection coatings 232 shown in FIGS. 13A-13H are full rounded coatings (e.g., as illustrated in FIG. 10C) and the edge protection coatings 232 shown in FIGS. 16A-16H are full straight edge coatings (e.g., as illustrated in FIG. 10A). FIG. 16A provides an illustration similar to that of FIG. 13A, except where the edge protection coating 232 shown in FIG. 16A is a straight edge coating. FIG. 16B provides an illustration similar to that of FIG. 13B, except where the edge protection coating 232 shown in FIG. 16B is a straight edge coating. FIG. 16C provides an illustration similar to that of FIG. 13C, except where the edge protection coating 232 shown in FIG. 16C is a straight edge coating. FIG. 16D provides an illustration similar to that of FIG. 13D, except where the edge protection coating 232 shown in FIG. 16D is a straight edge coating. FIG. 16E provides an illustration similar to that of FIG. 13E, except where the edge protection coating 232 shown in FIG. 16E is a straight edge coating. FIG. 16F provides an illustration similar to that of FIG. 13F, except where the edge protection coating 232 shown in FIG. 16F is a straight edge coating. FIG. 16G provides an illustration similar to that of FIG. 13G, except where the edge protection coating 232 shown in FIG. 16G is a straight edge coating. FIG. 16H provides an illustration similar to that of FIG. 13H, except where the edge protection coating 232 shown in FIG. 16H is a straight edge coating.
FIGS. 17A-17G provide cross-sectional side views illustrating portions of the microelectronic assemblies (e.g., the microelectronic assemblies 100) with variations in combinations of glass cores 110, build-up layers 210, and edge protection coatings 232 with different edge shapes where the edge protection coatings 232 are full chamfered coatings, according to some embodiments of the present disclosure. FIGS. 17A-17G are similar to FIGS. 12A-12G, except that the edge protection coatings 232 shown in FIGS. 12A-12G are partial coatings and the edge protection coatings 232 shown in FIGS. 17A-17G are full coatings. FIG. 17A provides an illustration similar to that of FIG. 12A, except where the edge protection coating 232 shown in FIG. 17A is a full coating. FIG. 17B provides an illustration similar to that of FIG. 12B, except where the edge protection coating 232 shown in FIG. 17B is a full coating. FIG. 17C provides an illustration similar to that of FIG. 12C, except where the edge protection coating 232 shown in FIG. 17C is a full coating. FIG. 17D provides an illustration similar to that of FIG. 12D, except where the edge protection coating 232 shown in FIG. 17D is a full coating. FIG. 17E provides an illustration similar to that of FIG. 12E, except where the edge protection coating 232 shown in FIG. 17E is a full coating. FIG. 17F provides an illustration similar to that of FIG. 12F, except where the edge protection coating 232 shown in FIG. 17F is a full coating. FIG. 17G provides an illustration similar to that of FIG. 12G, except where the edge protection coating 232 shown in FIG. 17G is a full coating.
FIGS. 18A-18H provide cross-sectional side views illustrating portions of the microelectronic assemblies (e.g., the microelectronic assemblies 100) with variations in combinations of glass cores 110, build-up layers 210, and edge protection coatings 232 with different edge shapes where the edge protection coatings 232 are partial straight edge coatings, according to some embodiments of the present disclosure. FIGS. 18A-18H are similar to FIGS. 16A-16H, except that the edge protection coatings 232 shown in FIGS. 16A-16H are full coatings and the edge protection coatings 232 shown in FIGS. 18A-18H are partial coatings. FIG. 18A provides an illustration similar to that of FIG. 16A, except where the edge protection coating 232 shown in FIG. 18A is a partial coating. FIG. 18B provides an illustration similar to that of FIG. 16B, except where the edge protection coating 232 shown in FIG. 18B is a partial coating. FIG. 18C provides an illustration similar to that of FIG. 16C, except where the edge protection coating 232 shown in FIG. 18C is a partial coating. FIG. 18D provides an illustration similar to that of FIG. 16D, except where the edge protection coating 232 shown in FIG. 18D is a partial coating. FIG. 18E provides an illustration similar to that of FIG. 16E, except where the edge protection coating 232 shown in FIG. 18E is a partial coating. FIG. 18F provides an illustration similar to that of FIG. 16F, except where the edge protection coating 232 shown in FIG. 18F is a partial coating. FIG. 18G provides an illustration similar to that of FIG. 16G, except where the edge protection coating 232 shown in FIG. 18G is a partial coating. FIG. 18H provides an illustration similar to that of FIG. 16H, except where the edge protection coating 232 shown in FIG. 18G is a partial coating.
An example of edge features in the form of frame protection is shown in FIGS. 19A-19, showing, respectively, top-down and cross-sectional side views of a glass core 110 with a frame 242, according to some embodiments of the present disclosure. In FIG. 19A, a dashed contour illustrates a portion 240 of the glass core 110 for which an example of cross-sectional side view is shown in FIG. 19B. As shown in FIG. 19A, in some embodiments, the frame 242 may extend around all edges 194 of the glass core 110. FIG. 19B illustrates that such a frame 242 may wrap around the edges 194 in that it may have a first portion 244-1 on the first face 190-1 of the glass core 110, a second portion 244-2 on the second face 190-2 of the glass core 110, and a third portion 244-3 on the edge 194, connecting the first portion 244-1 and the second portion 244-2. Collectively, any two or more of the portions 244-1, 244-2, and 244-3 may be referred to as “portions 244.” The frame 242 may act as a clamp, clamping the edge regions 196 to keep edges 194 under compression. In various embodiments, the frame 242 may include any of the materials described with reference to the edge protection coatings 202, 212, 222, and 232. While FIGS. 19A-19B illustrate the frame 242 in the edge regions 196 of a glass core 110, the frame 242 as described herein may also be provided in the edge regions of a glass panel 182 (e.g., around multiple glass cores 110). Thus, the frame 242 as described herein may be provided in the periphery (i.e., in the edge regions) of a glass panel 182 that includes two or more individual glass units 186 or individual glass cores 110.
Turning to the edge features based on glass edge treatment after singulation, FIGS. 20-23 illustrate top-down (FIGS. 20A, 21A, 22A, and 23A) and cross-sectional side (FIGS. 20B, 21B, 22B, and 23B) views of a glass core to which a glass edge treatment has been applied, according to different embodiments.
FIGS. 20A-20B provide top-down and cross-sectional side views of a glass core 110 to which a thermal treatment in the form of heating and cooling glass edges has been applied, according to some embodiments of the present disclosure. Application of a thermal treatment in the form of heating and cooling the edges 194 of the glass core 110 results in creation of an edge surface region 252 and a bulk region 254 with different characteristics. In some embodiments, the thermal treatment in the form of heating and cooling glass edges may include heating the glass core 110 to a temperature above the glass transition temperature of the glass core 110, possibly close to the melting point of the glass core 110, and then rapidly cooling of the glass core 110. In some embodiments, the cooling may be performed in air, while, in other embodiments, the cooling may be performed using cooling devices. At the beginning of the cooling process the surface of the edges 194 may cool down and contract quickly, while the inner region of the glass core 110 may remain hot to compensate dimensional changes with small relaxation stress. In this condition, the inner region of the glass core 110 is subject to compression while the external one is in tension. When the interior of the glass core 110 cools and contracts, the surfaces are already rigid and therefore residual tensile stresses may be created inside the glass core 110 (e.g., in the bulk region 254) while compressive stresses occur at the surface (e.g., in the edge surface region 252). In comparison to a simple annealed glass, this thermal tempering process may increase the strength of the pristine glass material because the applied stresses overcome the residual compressive ones on the surface, thus reducing crack formation and/or propagation.
In FIG. 20A, a dashed contour illustrates a portion 250 of the glass core 110 for which an example of cross-sectional side view is shown in FIG. 20B. As shown in FIG. 20, the edge surface region 252 may be a region extending along the edges 194, where the edge surface region 252 is different from the rest of the glass core 110, and the rest of the glass core 110 may be referred to as a “bulk region 254.” The edge surface region 254 may be a portion of the glass core 110 that starts at the surface of an edge 194 and extends from the surface into the glass core 110 by a depth 253. The bulk region 254 is a portion of the glass core 110 further away from the edges 194 than the edge surface region 252. The depth 253 may be between a few nanometers and about 50 micron, e.g., between about 50 nanometers and 50 micron, or between about 1 micron and 50 micron. In some embodiments, the density of the edge surface region 252 may be higher than the density of the bulk region 254, e.g., at least about 5% higher or at least about 7.5% higher. In some embodiments, the edge surface region 252 and the bulk region 254 may be different in terms of their hardness and/or toughness. More generally, in various embodiments, a microstructure of the edge surface region 252 may be different from a microstructure of the bulk region 254, which may be different in terms of one or more of density, phase composition, defects and dislocations, texture, hardness characteristics, or toughness characteristics. In some embodiments, an interface 256 may be noticeable in a cross-section of the glass core 110, where the interface 256 is where regions having different microstructures (i.e., the edge surface region 252 and the bulk region 254) meet.
FIGS. 21A-21B provide top-down and cross-sectional side views of a glass core 110 to which a thermal treatment in the form of laser peening has been applied, according to some embodiments of the present disclosure. Application of a thermal treatment in the form of laser peening of the edges 194 of the glass core 110 results in creation of an edge surface region 262 and a bulk region 264 with different characteristics. In some embodiments, the thermal treatment in the form of laser peening may involve the use of a high-energy laser to generate shock waves on the surface of the edges 194 of the glass core 110. These shock waves may create compressive residual stresses in the edge surface region 262 of the glass core 110, which can enhance its fatigue resistance, strength, and other mechanical properties. In some embodiments, laser peening may include scanning a laser beam along the surface of an edge 194. Wavelengths that may be used for laser irradiation of the glass core 110 may be between about 200 nanometers and 1600 nanometers. Laser irradiation may also be referred to as “laser polishing” because it may reduce the surface roughness of the surfaces of the edges 194 of the glass core 110. As a result of laser peening, portions of the surfaces of the edges 194 onto which the laser beam is directed may be melted and re-solidified, resulting in different material characteristics between the edge surface region 262 and the bulk region 264.
In FIG. 21A, a dashed contour illustrates a portion 260 of the glass core 110 for which an example of cross-sectional side view is shown in FIG. 21B. As shown in FIG. 21, the edge surface region 262 may be a region extending along the edges 194, where the edge surface region 262 is different from the rest of the glass core 110, and the rest of the glass core 110 may be referred to as a “bulk region 264.” The edge surface region 264 may be a portion of the glass core 110 that starts at the surface of an edge 194 and extends from the surface into the glass core 110 by a depth 263. The bulk region 264 is a portion of the glass core 110 further away from the edges 194 than the edge surface region 262. The depth 263 may be between a few nanometers and about 10 micron, e.g., between about 1 nanometer and 10 micron, or between about 10 nanometers and 1000 nanometers. In some embodiments, the density of the edge surface region 262 may be higher than the density of the bulk region 264, e.g., at least about 5% higher or at least about 7.5% higher. In some embodiments, the edge surface region 262 and the bulk region 264 may be different in terms of their hardness and/or toughness. More generally, in various embodiments, a microstructure of the edge surface region 262 may be different from a microstructure of the bulk region 264, which may be different in terms of one or more of density, phase composition, defects and dislocations, texture, hardness characteristics, or toughness characteristics. In some embodiments, an interface 266 may be noticeable in a cross-section of the glass core 110, where the interface 266 is where regions having different microstructures (i.e., the edge surface region 262 and the bulk region 264) meet. Different from the edge surface region 254 where heating was applied uniformly to all portions of the surface of the edges 194, in some embodiments, the edge surface region 262 may exhibit characteristic pockets 268 of glass material with different microstructures than the bulk region 264. The pockets 268 are portions of the surfaces of the edges 194 onto which the laser beam is directed during laser scanning, and may be portions of melted and re-solidified materials of the glass core 110. In various embodiments, the pockets 268 may be overlapping with one another, adjacent to and in contact with one another, or separated by regions of the glass core 110 which were not melted and re-solidified.
FIGS. 22A-22B provide top-down and cross-sectional side views of a glass core 110 to which a thermal treatment by means of an ultrafast laser has been applied, according to some embodiments of the present disclosure. Application of a thermal treatment in the form of an ultrafast laser results in creation of an edge surface region 272 and a bulk region 274 with different characteristics. In FIG. 22A, a dashed contour illustrates a portion 270 of the glass core 110 for which an example of cross-sectional side view is shown in FIG. 22B. When an ultrafast laser pulse is focused into a dielectric material like glass, it may be absorbed through nonlinear processes such as multiphoton absorption or avalanche ionization. Permanent strain may be generated in the focal region, through structural change, void formation, nanograting formation, and thermal flow effects. Ultrafast laser-induced stress may be tensile or compressive depending on laser pulse energy, repetition rate, polarization, and write speed. Application of an ultrafast laser is similar to laser shock peening, but the laser is focused at several points within the glass core 110 and not just at the surface of the edges 194. Thus, unlike the edge surface region 262, the edge surface region 272 does not start at the edges 194, but is embedded under the surface of the edges 194. As shown in FIG. 22, the edge surface region 272 may be separated from the edges 194 by a separation region 275, which may include an unmodified glass material of the glass core 110, similar to the material of the bulk region 274. As a result of using an ultrafast laser, portions of the glass core 110 onto which the laser beam is focused may be melted and re-solidified, resulting in different material characteristics between the edge surface region 272 and those of the bulk region 274 and the separation region 275. In some embodiments, a width 273 of the edge surface region 272 may be substantially the same as the depth 263, described above. In some embodiments, a depth 277 of the separation region 275 may also be substantially the same as the depth 263, described above. In some embodiments, the density of the edge surface region 272 may be higher than the density of the bulk region 274 and higher than the density of the separation region 275, e.g., at least about 5% higher or at least about 7.5% higher. Other descriptions of the edge surface region 262 and the bulk region 264 are applicable to the edge surface region 272 and the bulk region 274. In some embodiments, interfaces 276 may be noticeable in a cross-section of the glass core 110, where the interfaces 276 are interfaces where regions having different microstructures meet (e.g., where the edge surface region 272 and the bulk region 274 meet, or where edge surface region 272 and the separation region 275 meet). In some embodiments, application of an ultrafast laser may include scanning a laser beam along the edges 194. Thus, similar to the edge surface region 264, in some embodiments, the edge surface region 272 may exhibit characteristic pockets 278 of glass material with different microstructures than the bulk region 274 or the separation region 275. The pockets 278 are portions of the glass core 110 onto which the ultrafast laser beam is directed during laser scanning, and may be portions of melted and re-solidified materials of the glass core 110. Similar to the pockets 268, in various embodiments, the pockets 278 may be overlapping with one another, adjacent to and in contact with one another, or separated by regions of the glass core 110 which were not melted and re-solidified.
FIGS. 23A-23B provide top-down and cross-sectional side views of a glass core 110 to which a chemical treatment has been applied, according to some embodiments of the present disclosure. The cross-sectional side views shown in FIG. 23B is a cross-section along a plane AA shown in the top-down view of FIG. 23A. Application of a chemical treatment results in creation of an edge surface region 282 and a bulk region 284 with different characteristics. The edge surface region 284 may be a portion of the glass core 110 that starts at the surface of an edge 194 and extends from the surface into the glass core 110 by a depth 283. The bulk region 284 is a portion of the glass core 110 further away from the edges 194 than the edge surface region 282. The depth 283 may be between a few nanometers and about 50 micron, e.g., between about 50 nanometers and 50 micron, or between about 1 micron and 50 micron. In some embodiments, the chemical treatment may include performing ion exchange. The ion exchange may be performed by replacing original ions 286 present in the solid material of the glass core 110 with replacement ions 288 provided from a solution or vapor around the glass core 110. The ion exchange may take place at or near the surface of the edges 194 and, as a result, the edge surface region 282 may be a region that includes both the original ions 286 and the replacement ions 288, while the bulk region 284 may be a region that includes the original ions 286 but substantially no replacement ions 288 (e.g., an atomic concentration may be below about 1%), which means that the microstructure of the edge surface region 282 is different from the microstructure of the bulk region 284. In some embodiments, the original ions 286 may include ions of silicon, sodium, potassium, or aluminum. In some embodiments, the original ions 286 may be smaller than the replacement ions 288, e.g., smaller by at least about 10% or smaller by at least about 50% than the average dimensions of the replacement ions 288. In some embodiments, an atomic concentration of the replacement ions 288 in the edge surface region 282 may be smaller than that of the original ions 286, e.g., the atomic concentration of the replacement ions 288 in the edge surface region 282 may be smaller than about 20%, or smaller than about 10%, than that of the original ions 286, but larger than the atomic concentrations of such ions that may be present as an accidental impurity. For example, in some embodiments, an atomic concentration of the replacement ions 288 in the edge surface region 282 may be at least 2%, e.g., at least 5% or at least 10% or at least 15%. In some embodiments, a density of the edge surface region 282 may be higher than the density of the bulk region 284, e.g., at least about 5% higher or at least about 7.5% higher.
Various edge features described above may, advantageously, be easily fabricated in parallel with conventional manufacturing techniques for glass core substrates. Various arrangements of the microelectronic assemblies 100 and glass cores 110 as shown in FIGS. 1-23 do not represent an exhaustive set of microelectronic assemblies and glass cores in which various edge features as described herein may be used, but merely provide some illustrative examples. In particular, the number and positions of various elements shown in FIGS. 1-23 is purely illustrative and, in various other embodiments, other numbers of these elements, provided in other locations relative to one another may be used in accordance with the general architecture considerations described herein. For example, although not specifically shown in the present drawings, in some embodiments, a microelectronic assembly 100 may include a redistribution layer (RDL) between any pair of layers shown in FIG. 1 and FIG. 2, the RDL including a plurality of interconnect structures (e.g., conductive lines and conductive vias) to assist routing of signals and/or power between components. In another example, although also not specifically shown in the present drawings, in some embodiments, a package substrate 102 of a microelectronic assembly 100 may include one or more recesses. In such embodiments, a bottom face of a recess in the package substrate 102 may be provided by the solid material of the package substrate 102. A recess may be formed in a package substrate 102 in any suitable manner (e.g., via three-dimensional printing, laser cutting or drilling the recess into an existing package substrate, etc.). At least a portion of the substrate 107 or the glass core 110 may be positioned over or at least partially in such a recess. In yet another example, features of any one of FIGS. 1-23 may be combined with features of any other one of FIGS. 1-23.
The microelectronic assemblies 100 and/or the glass cores 110 disclosed herein, in particular the glass cores 110 with one or more edge features as described herein, may be included in any suitable electronic component. FIGS. 24-27 illustrate various examples of apparatuses that may include, or be included in, any of the microelectronic assemblies 100 and/or the glass cores 110 disclosed herein.
FIG. 24 is a top view of a wafer 1500 and dies 1502 that may be included in any of the microelectronic assemblies 100 as described herein. For example, a die 1502 may be any of the dies 114 described herein. The wafer 1500 may be composed of semiconductor material and may include one or more dies 1502 having IC structures formed on a surface of the wafer 1500. Each of the dies 1502 may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer 1500 may undergo a singulation process in which the dies 1502 are separated from one another to provide discrete “chips” of the semiconductor product. The die 1502 may include one or more transistors (e.g., some of the transistors 1640 of FIG. 25, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer 1500 or the die 1502 may include a memory device (e.g., a random-access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on a same die 1502 as a processing device (e.g., the processing device 1802 of FIG. 27) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.
FIG. 25 is a side, cross-sectional view of an IC device 1600 that may be included in any of the microelectronic assemblies 100 as described herein. For example, an IC device 1600 may be provided on/in any of the dies 114 described herein. The IC device 1600 may be formed on a substrate 1602 (e.g., the wafer 1500 of FIG. 24) and may be included in a die (e.g., the die 1502 of FIG. 24). The substrate 1602 may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The substrate 1602 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate 1602 may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group III-V materials (i.e., materials from groups III and V of the periodic system of elements), group II-VI (i.e., materials from groups Il and IV of the periodic system of elements), or group IV materials (i.e., materials from group IV of the periodic system of elements) may also be used to form the substrate 1602. Although a few examples of materials from which the substrate 1602 may be formed are described here, any material that may serve as a foundation for an IC device 1600 may be used. The substrate 1602 may be part of a singulated die (e.g., the dies 1502 of FIG. 24) or a wafer (e.g., the wafer 1500 of FIG. 24).
The IC device 1600 may include one or more device layers 1604 disposed on the substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in FIG. 25 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Planar transistors may include bipolar junction transistors (BJT), heterojunction bipolar transistors (HBT), or high-electron-mobility transistors (HEMT). Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.
Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top face of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top face of the substrate and does not include sidewall portions substantially perpendicular to the top face of the substrate. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1620 may be formed within the substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S/D regions 1620 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 1602 to form the S/D regions 1620. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 1602 may follow the ion-implantation process. In the latter process, the substrate 1602 may first be etched to form recesses at the locations of the S/D regions 1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1620. In some implementations, the S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in-situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1620 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1620.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., the transistors 1640) of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in FIG. 25 as interconnect layers 1606, 1608, and 1610). For example, electrically conductive features of the device layer 1604 (e.g., the gate 1622 and the S/D contacts 1624) may be electrically coupled with the interconnect structures 1628 of the interconnect layers 1606, 1608, and 1610. The one or more interconnect layers 1606, 1608, and 1610 may form a metallization stack (also referred to as an “ILD stack”) 1619 of the IC device 1600.
The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in FIG. 25). Although a particular number of interconnect layers 1606, 1608, and 1610 is depicted in FIG. 25, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.
In some embodiments, the interconnect structures 1628 may include lines 1628a and/or vias 1628b filled with an electrically conductive material such as a metal. The lines 1628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 1602 upon which the device layer 1604 is formed. For example, the lines 1628a may route electrical signals in a direction in and out of the page from the perspective of FIG. 25. The vias 1628b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 1602 upon which the device layer 1604 is formed. In some embodiments, the vias 1628b may electrically couple lines 1628a of different interconnect layers 1606, 1608, and 1610 together.
The interconnect layers 1606, 1608, and 1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in FIG. 25. In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different ones of the interconnect layers 1606, 1608, and 1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606, 1608, and 1610 may be the same.
A first interconnect layer 1606 may be formed above the device layer 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. The lines 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., the S/D contacts 1624) of the device layer 1604.
A second interconnect layer 1608 may be formed above the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the lines 1628a and the vias 1628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
A third interconnect layer 1610 (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device layer 1604) may be thicker.
The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606, 1608, and 1610. In FIG. 25, the conductive contacts 1636 are illustrated as taking the form of bond pads. The conductive contacts 1636 may be electrically coupled with the interconnect structures 1628 and configured to route the electrical signals of the transistor(s) 1640 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 1636 to mechanically and/or electrically couple a chip including the IC device 1600 with another component (e.g., a circuit board). The IC device 1600 may include additional or alternate structures to route the electrical signals from the interconnect layers 1606, 1608, and 1610; for example, the conductive contacts 1636 may include other analogous features (e.g., posts) that route the electrical signals to external components.
FIG. 26 is a side, cross-sectional view of an IC device assembly 1700 that may include a glass core with one or more edge features in accordance with any of the embodiments disclosed herein. The IC device assembly 1700 includes a number of components disposed on a circuit board 1702 (which may be, e.g., a motherboard). The IC device assembly 1700 includes components disposed on a first face 1740 of the circuit board 1702 and an opposing second face 1742 of the circuit board 1702; generally, components may be disposed on one or both faces 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may take the form of any of the embodiments of the microelectronic assemblies 100 discussed above, e.g., may include one or more microelectronic assemblies 100 as discussed with reference to FIG. 1 and FIG. 2, and/or may include one or more glass cores as discussed with reference to FIGS. 3-23.
In some embodiments, the circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.
The IC device assembly 1700 illustrated in FIG. 26 includes a package-on-interposer structure 1736 coupled to the first face 1740 of the circuit board 1702 by coupling components 1716. The coupling components 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702, and may include solder balls (as shown in FIG. 26), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.
The package-on-interposer structure 1736 may include an IC package 1720 coupled to a package interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in FIG. 26, multiple IC packages may be coupled to the package interposer 1704; indeed, additional interposers may be coupled to the package interposer 1704. The package interposer 1704 may provide an intervening substrate used to bridge the circuit board 1702 and the IC package 1720. The IC package 1720 may be or include, for example, a die (the die 1502 of FIG. 5), an IC device (e.g., any of the IC devices described herein, or any combination of such IC devices), or any other suitable component. Generally, the package interposer 1704 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the package interposer 1704 may couple the IC package 1720 (e.g., a die) to a set of ball grid array (BGA) conductive contacts of the coupling components 1716 for coupling to the circuit board 1702. In the embodiment illustrated in FIG. 26, the IC package 1720 and the circuit board 1702 are attached to opposing sides of the package interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to a same side of the package interposer 1704. In some embodiments, three or more components may be interconnected by way of the package interposer 1704.
In some embodiments, the package interposer 1704 may be formed as a glass core with one or more edge features, e.g., as any embodiment of the glass core 110, described herein. In some embodiments, the package interposer 1704 may be formed as a PCB. In some embodiments, the package interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the package interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. In any of these embodiments, the package interposer 1704 may include multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The package interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to conductive vias 1706. If the package interposer 1704 is a glass core, e.g., the glass core 110 as described herein, then the conductive vias 1706 may be TGVs 115 as described herein. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.
The IC device assembly 1700 illustrated in FIG. 26 includes a package-on-package structure 1734 coupled to the second face 1742 of the circuit board 1702 by coupling components 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by coupling components 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling components 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The package-on-package structure 1734 may be configured in accordance with any of the package-on-package structures known in the art.
FIG. 27 is a block diagram of an example communication device 1800 that may include one or more microelectronic assemblies 100 and/or one or more glass cores 110 in accordance with any of the embodiments disclosed herein. A handheld communication device or a laptop communication device may be examples of the communication device 1800. Any suitable ones of the components of the communication device 1800 may include one or more of the microelectronic assemblies 100, IC packages 1720, 1724, IC device assemblies 1700, IC devices 1600, or dies 1502 disclosed herein. In particular, any suitable ones of the components of the communication device 1800 may include one or more glass cores 110 as described herein, e.g., as a part of a microelectronic assembly 100 as described herein. A number of components are illustrated in FIG. 27 as included in the communication device 1800, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the communication device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.
Additionally, in various embodiments, the communication device 1800 may not include one or more of the components illustrated in FIG. 27, but the communication device 1800 may include interface circuitry for coupling to the one or more components. For example, the communication device 1800 may not include a display device 1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1806 may be coupled. In another set of examples, the communication device 1800 may not include an audio input device 1824 or an audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1824 or audio output device 1808 may be coupled.
The communication device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The communication device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic RAM (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).
In some embodiments, the communication device 1800 may include a communication module 1812 (e.g., one or more communication modules). For example, the communication module 1812 may be configured for managing wireless communications for the transfer of data to and from the communication device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication module 1812 may be, or may include, any of the microelectronic assemblies 100 disclosed herein.
The communication module 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication module 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication module 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication module 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication module 1812 may operate in accordance with other wireless protocols in other embodiments. The communication device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions). The antenna 1822 may include one or more microelectronic assemblies 100 and/or one or more glass cores 110 as described herein, e.g., as a part of a microelectronic assembly 100 as described herein.
In some embodiments, the communication module 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication module 1812 may include multiple communication modules. For instance, a first communication module 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication module 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication module 1812 may be dedicated to wireless communications, and a second communication module 1812 may be dedicated to wired communications. In some embodiments, the communication module 1812 may support millimeter wave communication.
The communication device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the communication device 1800 to an energy source separate from the communication device 1800 (e.g., AC line power).
The communication device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The communication device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The communication device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The communication device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the communication device 1800, as known in the art.
The communication device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The communication device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The communication device 1800 may have any desired form factor, such as a handheld or mobile communication device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop communication device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable communication device. In some embodiments, the communication device 1800 may be any other electronic device that processes data.
The following paragraphs provide examples of various ones of the embodiments disclosed herein.
Example 1 provides a microelectronic assembly that includes a glass core (e.g., a layer of glass including a rectangular prism volume) having a first face, a second face opposite the first face, and an edge between an end of the first face and an end of the second face; and a protection coating on the edge.
Example 2 provides the microelectronic assembly according to example 1, further including a build-up layer over the first face of the glass core, the build-up layer including a dielectric material and conductive pathways (e.g., conductive traces and/or conductive vias) extending through the dielectric material, where the protection coating is further on an edge of the build-up layer.
Example 3 provides the microelectronic assembly according to example 2, where the protection coating on the edge of the build-up layer is materially continuous with the protection coating on the edge of the glass core.
Example 4 provides the microelectronic assembly according to example 2, where the protection coating is further on a face (e.g., on the top or on the bottom) of the build-up layer.
Example 5 provides the microelectronic assembly according to example 4, where the protection coating on the face of the build-up layer is materially continuous with the protection coating on the edge of the build-up layer.
Example 6 provides the microelectronic assembly according to example 5, where the protection coating on the edge of the build-up layer is materially continuous with the protection coating on the edge of the glass core.
Example 7 provides the microelectronic assembly according to any one of examples 2-6, where the edge of the glass core protrudes from the edge of the build-up layer.
Example 8 provides the microelectronic assembly according to any one of examples 2-6, where the edge of the glass core is aligned with (e.g., does not protrude from) the edge of the build-up layer.
Example 9 provides the microelectronic assembly according to any one of examples 2-8, where the edge of the build-up layer is substantially straight.
Example 10 provides the microelectronic assembly according to any one of examples 2-8, where the edge of the build-up layer is chamfered.
Example 11 provides the microelectronic assembly according to example 1, further including a build-up layer over the first face of the glass core, the build-up layer including a dielectric material and conductive pathways (e.g., conductive traces and/or conductive vias) extending through the dielectric material, where the protection coating is absent from an edge or a face of the build-up layer.
Example 12 provides the microelectronic assembly according to any one of examples 1-11, where the edge of the glass core is substantially straight.
Example 13 provides the microelectronic assembly according to any one of examples 1-11, where the edge of the glass core is chamfered.
Example 14 provides the microelectronic assembly according to any one of examples 1-11, where the edge of the glass core is rounded.
Example 15 provides the microelectronic assembly according to any one of examples 1-14, where an edge of the protection coating is substantially straight.
Example 16 provides the microelectronic assembly according to any one of examples 1-14, where an edge of the protection coating is chamfered.
Example 17 provides the microelectronic assembly according to any one of examples 1-14, where an edge of the protection coating is rounded.
Example 18 provides the microelectronic assembly according to any one of the preceding examples, where the protection coating includes solder resist.
Example 19 provides the microelectronic assembly according to any one of the preceding examples, where the protection coating includes a photo-imageable dielectric.
Example 20 provides the microelectronic assembly according to any one of the preceding examples, where the protection coating includes an organic insulator material.
Example 21 provides the microelectronic assembly according to any one of the preceding examples, where the protection coating includes an inorganic insulator material.
Example 22 provides the microelectronic assembly according to any one of the preceding examples, where the protection coating includes a polymer.
Example 23 provides the microelectronic assembly according to any one of the preceding examples, where the protection coating includes a material with a Young's modulus smaller than about 10 GPa.
Example 24 provides the microelectronic assembly according to any one of the preceding examples, where the protection coating includes a material with a CTE smaller than about 15 ppm/K, e.g., smaller than about 10 ppm/K or smaller than about 5 ppm/K.
Example 25 provides the microelectronic assembly according to any one of the preceding examples, where the protection coating includes an electrically conductive material.
Example 26 provides the microelectronic assembly according to any one of the preceding examples, where the protection coating includes a metal.
Example 27 provides the microelectronic assembly according to any one of the preceding examples, where the protection coating includes a crack-healing material.
Example 28 provides the microelectronic assembly according to example 27, where the crack-healing material includes a matrix material and particles dispersed in the matrix material, the particles containing a crack-healing agent.
Example 29 provides the microelectronic assembly according to example 28, where the crack-healing material includes a polymer.
Example 30 provides the microelectronic assembly according to examples 28 or 29, where the crack-healing agent includes poly (urea-formaldehyde) (PUF), polyurethane, poly (melamine-urea-formaldehyde) (PMUF), or poly (melamine-formaldehyde) (PMF).
Example 31 provides the microelectronic assembly according to any one of examples 28-30, where the matrix material includes a thermoset (e.g., one or more of a phenolic, an alkyd, a vinyl ester, an unsaturated polyester, a polyurethane, or an aminoplastic).
Example 32 provides the microelectronic assembly according to any one of examples 28-31, where an individual particle of the particles includes a shell, and the crack-healing agent is within the shell.
Example 33 provides the microelectronic assembly according to example 32, where the shell is a ceramic.
Example 34 provides the microelectronic assembly according to examples 32 or 33, where the shell includes silicon and oxygen.
Example 35 provides the microelectronic assembly according to any one of examples 28-34, where the crack-healing agent includes monomers and/or oligomers.
Example 36 provides the microelectronic assembly according to any one of examples 28-35, further including a catalyst, where the catalyst includes ruthenium.
Example 37 provides the microelectronic assembly according to example 36, where the catalyst is dispersed in the glass core.
Example 38 provides the microelectronic assembly according to examples 36 or 37, where the catalyst is on an edge of the glass core.
Example 39 provides the microelectronic assembly according to any one of examples 36-38, where the catalyst is in the matrix material.
Example 40 provides the microelectronic assembly according to any one of examples 36-39, where the catalyst is on an outer shell of the particles.
Example 41 provides a microelectronic assembly that includes a glass core (e.g., a layer of glass including a rectangular prism volume) having a first face, a second face opposite the first face, and an edge between an end of the first face and an end of the second face; and a clamp structure (e.g., a frame) around the edge, the clamp structure having a first portion at the first face, a second portion at the second face, and a third portion at the edge, where the third portion is attached to the first portion and the second portion.
Example 42 provides the microelectronic assembly according to example 41, where the third portion is materially continuous with the first portion and the second portion.
Example 43 provides the microelectronic assembly according to examples 41 or 42, where the first portion extends over the first face to a distance from the edge that is less than about 10% (e.g., less than about 5% or less than about 1%) of a width of the glass core.
Example 44 provides the microelectronic assembly according to any one of examples 41-44, where the clamp structure extends along at least 50% of a length of the edge.
Example 45 provides the microelectronic assembly according to any one of examples 41-44, where the clamp structure extends along an entire length of the edge.
Example 46 provides the microelectronic assembly according to any one of examples 41-45, further including a frame, where: the clamp structure is one of a plurality of clamp structures, the edge is one of a plurality of edges of the glass core, the frame includes the plurality of clamp structures connected in a ring along the plurality of edges of the glass core.
Example 47 provides the microelectronic assembly according to any one of examples 41-46, where the clamp structure includes an inorganic insulator material.
Example 48 provides the microelectronic assembly according to any one of examples 41-47, where the clamp structure includes a polymer.
Example 49 provides the microelectronic assembly according to any one of examples 41-48, where the clamp structure includes a material with a CTE smaller than about 15 ppm/K, e.g., smaller than about 10 ppm/K or smaller than about 5 ppm/K. 50. The microelectronic assembly according to any one of examples 41-49, where the clamp structure includes any of the materials of the protection coating of the preceding examples.
Example 51 provides a microelectronic assembly that includes a glass core (e.g., a layer of glass including a rectangular prism volume) having an edge surface region and a bulk region; and a component coupled to the glass core, where: the component is one of an IC die, a package substrate, or a redistribution layer, the edge surface region is either a portion of the glass core that starts at a surface of an edge of the glass core and extends from the surface into the glass core by a total depth between about 1 micron and 500 micron, or is a portion of the glass core that is spaced apart from the surface and extends into the glass by a total depth between about 1 micron and 500 micron, the bulk region is a portion of the glass core further away from the surface than the edge surface region, and a microstructure of the edge surface region is different from a microstructure of the bulk region.
Example 52 provides the microelectronic assembly according to example 51, where the edge surface region is the portion of the glass core that is spaced apart from the surface, and a spacing between the surface and the edge surface region is between about 1 micron and 500 micron.
Example 53 provides the microelectronic assembly according to examples 51 or 52, where the microstructure of the edge surface region being different from the microstructure of the bulk region includes a density of the edge surface region being higher than a density of the bulk region, e.g., at least about 5% higher or at least about 7.5% higher. In some embodiments, an atomic concentration of the ions of the material in the bulk region may be below 0.05%.
Example 54 provides the microelectronic assembly according to any one of examples 51-53, where the microstructure of the edge surface region being different from the microstructure of the bulk region includes a concentration of ions of a material in the edge surface region being higher than a concentration of ions of the material in the bulk region.
Example 55 provides the microelectronic assembly according to example 54, where the material is a first material, the edge surface region further includes ions of a second material, and the bulk region includes ions of the second material.
Example 56 provides the microelectronic assembly according to example 55, where the second material is one or more of silicon, sodium, potassium, or aluminum.
Example 57 provides the microelectronic assembly according to examples 55 or 55, where an atomic concentration of the first material in the edge surface region is smaller than an atomic concentration of the second material in the edge surface region.
Example 58 provides the microelectronic assembly according to example 57, where the atomic concentration of the first material in the edge surface region is smaller than about 10% of the atomic concentration of the second material in the edge surface region.
Example 59 provides the microelectronic assembly according to any one of examples 54-58, where the atomic concentration of the first material in the edge surface region is least 2%, e.g., at least 5% or at least 10% or at least 15%.
Example 60 provides the microelectronic assembly according to any one of the preceding examples, where: the microelectronic assembly includes a glass panel including a plurality of glass cores, and the glass core is one of the plurality of glass cores.
Example 61 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a solid layer of glass.
Example 62 provides the microelectronic assembly according to any one of the preceding examples, where a cross-section of the glass core in a plane perpendicular to a surface of the component is substantially rectangular.
Example 63 provides the microelectronic assembly according to any one of the preceding examples, where a cross-section of the glass core in a plane parallel to a surface of the component is substantially rectangular.
Example 64 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including at least 23% silicon by weight.
Example 65 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including at least 26% oxygen by weight.
Example 66 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including at least 23% silicon by weight and at least 26% oxygen by weight.
Example 67 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including at least 5% aluminum by weight.
Example 68 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass that does not include an organic adhesive or an organic material.
Example 69 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass having a thickness in a range of 50 micron (um) to 1.4 millimeters (mm), a first length in a range of 10 mm to 250 mm, and a second length in a range of 10 mm to 250 mm, the first length perpendicular to the second length.
Example 70 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass having a thickness in a range of 50 μm to 1.4 mm.
Example 71 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass having a first length in a range of 10 mm to 250 mm, and a second length in a range of 10 mm to 250 mm, the first length perpendicular to the second length.
Example 72 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including a rectangular prism volume.
Example 73 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including a rectangular prism volume having a first side and a second side perpendicular to the first side, the first side having a length in a range of 10 mm to 250 mm and the second side having a length in a range of 10 mm to 250 mm.
Example 74 provides the microelectronic assembly according to any one of the preceding examples, where the glass core is a layer of glass including a rectangular prism volume and a via extending from a first side of the rectangular prism volume to a second side of the rectangular prism volume, the via including a metal.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
Patent Application
20250192070
