Ho-Yin Yiu

Person

Hong Kong, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Chip scale sensing chip package
- Patent number 9,853,074
- Issue date Dec 26, 2017
- Xintec Inc.
- Ho-Yin Yiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package and fabrication method thereof
- Patent number 9,831,185
- Issue date Nov 28, 2017
- Xintec Inc.
- Shih-Yi Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating chip package with laser
- Patent number 9,780,050
- Issue date Oct 3, 2017
- Xintec Inc.
- Ying-Nan Wen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package and manufacturing method thereof
- Patent number 9,768,067
- Issue date Sep 19, 2017
- Xintec Inc.
- Chien-Hung Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package and manufacturing method thereof
- Patent number 9,721,911
- Issue date Aug 1, 2017
- Xintec Inc.
- Ho-Yin Yiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip package having a laser stop structure
- Patent number 9,640,405
- Issue date May 2, 2017
- Xintec Inc.
- Ying-Nan Wen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package having a dual through hole redistribution layer structure
- Patent number 9,543,233
- Issue date Jan 10, 2017
- Xintec Inc.
- Chien-Hung Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package having extended depression for electrical connection a...
- Patent number 9,406,578
- Issue date Aug 2, 2016
- Xintec Inc.
- Ying-Nan Wen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package structure and method for forming the same
- Patent number 8,981,497
- Issue date Mar 17, 2015
- Xintec Inc.
- Ho-Yin Yiu
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Top via pattern for bond pad structure
- Patent number 7,323,784
- Issue date Jan 29, 2008
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ho-Yin Yiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optical sensor by using tunneling diode
- Patent number 6,693,317
- Issue date Feb 17, 2004
- Taiwan Semiconductor Manufacturing Company
- Ho-Yin Yiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a stress buffered bond pad
- Patent number 6,258,706
- Issue date Jul 10, 2001
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ho-Yin Yiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low leakage wire bond pad structure for integrated circuits
- Patent number 6,180,964
- Issue date Jan 30, 2001
- Taiwan Semiconductor Manufacturing Co., Ltd
- Ho-Yin Yiu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
- Publication number 20230081775
- Publication date Mar 16, 2023
- XINTEC INC.
- Hsin-Yi CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP SCALE SENSING CHIP PACKAGE
- Publication number 20170213865
- Publication date Jul 27, 2017
- XINTEC INC.
- Ho-Yin YIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
- Publication number 20170076981
- Publication date Mar 16, 2017
- XINTEC INC.
- Chien-Hung LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF
- Publication number 20170047455
- Publication date Feb 16, 2017
- XINTEC INC.
- Ho-Yin YIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE AND FABRICATION METHOD THEREOF
- Publication number 20170047300
- Publication date Feb 16, 2017
- XINTEC INC.
- Ying-Nan WEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE AND FABRICATION METHOD THEREOF
- Publication number 20160322305
- Publication date Nov 3, 2016
- XINTEC INC.
- Shih-Yi LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE AND FABRICATION METHOD THEREOF
- Publication number 20160229687
- Publication date Aug 11, 2016
- XINTEC INC.
- Ying-Nan WEN
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
CHIP PACKAGE AND FABRICATION METHOD THEREOF
- Publication number 20160204061
- Publication date Jul 14, 2016
- XINTEC INC.
- Ho-Yin YIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE AND FABRICATION METHOD THEREOF
- Publication number 20160190063
- Publication date Jun 30, 2016
- XINTEC INC.
- Ying-Nan WEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
- Publication number 20160133544
- Publication date May 12, 2016
- XINTEC INC.
- Chien-Hung LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
- Publication number 20160133588
- Publication date May 12, 2016
- XINTEC INC.
- Ho-Yin YIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME
- Publication number 20150255358
- Publication date Sep 10, 2015
- XINTEC INC.
- Ying-Nan WEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
- Publication number 20130020693
- Publication date Jan 24, 2013
- Xintec Inc.
- Ho-Yin Yiu
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Top via pattern for bond pad structure
- Publication number 20060208360
- Publication date Sep 21, 2006
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ho-Yin Yiu
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Chip scale sensing chip package

Chip package and fabrication method thereof

Method of fabricating chip package with laser

Chip package and manufacturing method thereof

Chip package and manufacturing method thereof

Chip package having a laser stop structure

Chip package having a dual through hole redistribution layer structure

Chip package having extended depression for electrical connection a...

Chip package structure and method for forming the same

Top via pattern for bond pad structure

Optical sensor by using tunneling diode

Method for fabricating a stress buffered bond pad

Low leakage wire bond pad structure for integrated circuits

Patents Applicationslast 30 patents

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

CHIP SCALE SENSING CHIP PACKAGE

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

SENSING CHIP PACKAGE AND A MANUFACTURING METHOD THEREOF

CHIP PACKAGE AND FABRICATION METHOD THEREOF

CHIP PACKAGE AND FABRICATION METHOD THEREOF

CHIP PACKAGE AND FABRICATION METHOD THEREOF

CHIP PACKAGE AND FABRICATION METHOD THEREOF

CHIP PACKAGE AND FABRICATION METHOD THEREOF

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME

CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Top via pattern for bond pad structure