Hsing-Ya Tsao

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
10T NVSRAM cell and cell operations
- Patent number 9,177,645
- Issue date Nov 3, 2015
- Aplus Flash Technology, Inc
- Hsing-Ya Tsao
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-voltage fast-write PMOS NVSRAM cell
- Patent number 9,177,644
- Issue date Nov 3, 2015
- Aplus Flash Technology, Inc
- Hsing-Ya Tsao
- G11 - INFORMATION STORAGE
Information Patent Grant
1T1b and 2T2b flash-based, data-oriented EEPROM design
- Patent number 9,177,658
- Issue date Nov 3, 2015
- Aplus Flash Technology, Inc
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-boosting program inhibit scheme in NAND design
- Patent number 9,171,627
- Issue date Oct 27, 2015
- APlus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-voltage page buffer to be used in NVM design
- Patent number 9,019,764
- Issue date Apr 28, 2015
- APlus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip HV and LV capacitors acting as the second back-up supplies...
- Patent number 9,001,583
- Issue date Apr 7, 2015
- APlus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
8T NVSRAM cell and cell operations
- Patent number 8,929,136
- Issue date Jan 6, 2015
- Aplus Flash Technology, Inc
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
1T1b and 2T2b flash-based, data-oriented EEPROM design
- Patent number 8,923,049
- Issue date Dec 30, 2014
- Aplus Flash Technology, Inc
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Universal timing waveforms sets to improve random access read and w...
- Patent number 8,634,241
- Issue date Jan 21, 2014
- APlus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash...
- Patent number 8,345,481
- Issue date Jan 1, 2013
- Aplus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Row-decoder and select gate decoder structures suitable for flashed...
- Patent number 8,295,087
- Issue date Oct 23, 2012
- Aplus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for inhibiting excess leakage current in unsel...
- Patent number 8,289,775
- Issue date Oct 16, 2012
- Aplus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Row-decoder and source-decoder structures suitable for erase in uni...
- Patent number 8,274,829
- Issue date Sep 25, 2012
- Aplus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory with a unified cell structure
- Patent number 8,237,212
- Issue date Aug 7, 2012
- Abedneja Assetts AG L.L.C.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash...
- Patent number 8,072,811
- Issue date Dec 6, 2011
- Aplus Flash Technology, Inc,
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory with a unified cell structure
- Patent number 7,915,092
- Issue date Mar 29, 2011
- Abedneja Assets AG L.L.C.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory with a unified cell structure
- Patent number 7,636,252
- Issue date Dec 22, 2009
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Monolithic, combo nonvolatile memory allowing byte, page and block...
- Patent number 7,372,736
- Issue date May 13, 2008
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Combination nonvolatile memory using unified technology with byte,...
- Patent number 7,349,257
- Issue date Mar 25, 2008
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Combination nonvolatile memory using unified technology with byte,...
- Patent number 7,339,824
- Issue date Mar 4, 2008
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Monolithic, combo nonvolatile memory allowing byte, page and block...
- Patent number 7,324,384
- Issue date Jan 29, 2008
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Monolithic, combo nonvolatile memory allowing byte, page and block...
- Patent number 7,289,366
- Issue date Oct 30, 2007
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Monolithic, combo nonvolatile memory allowing byte, page and block...
- Patent number 7,283,401
- Issue date Oct 16, 2007
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Combination nonvolatile memory using unified technology with byte,...
- Patent number 7,154,783
- Issue date Dec 26, 2006
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Combination nonvolatile memory using unified technology with byte,...
- Patent number 7,149,120
- Issue date Dec 12, 2006
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Monolithic, combo nonvolatile memory allowing byte, page and block...
- Patent number 7,120,064
- Issue date Oct 10, 2006
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Monolithic, combo nonvolatile memory allowing byte, page and block...
- Patent number 7,110,302
- Issue date Sep 19, 2006
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Monolithic, combo nonvolatile memory allowing byte, page and block...
- Patent number 7,102,929
- Issue date Sep 5, 2006
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Monolithic, combo nonvolatile memory allowing byte, page and block...
- Patent number 7,075,826
- Issue date Jul 11, 2006
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Monolithic, combo nonvolatile memory allowing byte, page and block...
- Patent number 7,064,978
- Issue date Jun 20, 2006
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN
- Publication number 20150071007
- Publication date Mar 12, 2015
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
8T NVSRAM CELL AND CELL OPERATIONS
- Publication number 20140119118
- Publication date May 1, 2014
- APLUS FLASH TECHNOLOGY, INC.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
10T NVSRAM CELL AND CELL OPERATIONS
- Publication number 20140112072
- Publication date Apr 24, 2014
- APLUS FLASH TECHNOLOGY, INC.
- Hsing-Ya Tsao
- G11 - INFORMATION STORAGE
Information Patent Application
ON-CHIP HV AND LV CAPACITORS ACTING AS THE SECOND BACK-UP SUPPLIES...
- Publication number 20140104946
- Publication date Apr 17, 2014
- APLUS FLASH TECHNOLOGY, INC.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
LOW-VOLTAGE FAST-WRITE PMOS NVSRAM CELL
- Publication number 20140050025
- Publication date Feb 20, 2014
- APLUS FLASH TECHNOLOGY, INC.
- Hsing-Ya Tsao
- G11 - INFORMATION STORAGE
Information Patent Application
LOW-VOLTAGE FAST-WRITE NVSRAM CELL
- Publication number 20130294161
- Publication date Nov 7, 2013
- APLUS FLASH TECHNOLOGY, INC.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
NON-BOOSTING PROGRAM INHIBIT SCHEME IN NAND DESIGN
- Publication number 20130272067
- Publication date Oct 17, 2013
- APLUS FLASH TECHNOLOGY, INC.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Three-Dimensional Flash-Based Combo Memory and Logic Design
- Publication number 20130215683
- Publication date Aug 22, 2013
- APLUS FLASH TECHNOLOGY, INC.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
NEW 1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN
- Publication number 20130182509
- Publication date Jul 18, 2013
- APLUS FLASH TECHNOLOGY, INC.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Low-Voltage Page Buffer to be Used in NVM Design
- Publication number 20130128667
- Publication date May 23, 2013
- APLUS FLASH TECHNOLOGY, INC.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Universal Timing Waveforms Sets to Improve Random Access Read and W...
- Publication number 20120155173
- Publication date Jun 21, 2012
- Peter Wung LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash...
- Publication number 20120044770
- Publication date Feb 23, 2012
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE MEMORY WITH A UNIFIED CELL STRUCTURE
- Publication number 20110170357
- Publication date Jul 14, 2011
- ABEDNEJA ASSETS AG L.L.C.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and method for inhibiting excess leakage current in unsel...
- Publication number 20090316487
- Publication date Dec 24, 2009
- Aplus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Row-decoder and select gate decoder structures suitable for flashed...
- Publication number 20090310405
- Publication date Dec 17, 2009
- Aplus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Row-decoder and source-decoder structures suitable for erase in uni...
- Publication number 20090310411
- Publication date Dec 17, 2009
- Aplus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
NAND based NMOS NOR flash memory cell, a NAND based NMOS nor flash...
- Publication number 20090279360
- Publication date Nov 12, 2009
- Aplus Flash Technology, Inc.
- Peter Wung Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Novel monolithic, combo nonvolatile memory allowing byte, page and...
- Publication number 20080247230
- Publication date Oct 9, 2008
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Novel monolithic, combo nonvolatile memory allowing byte, page and...
- Publication number 20080096327
- Publication date Apr 24, 2008
- Aplus Flash Technology Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Combination nonvolatile memory using unified technology with byte,...
- Publication number 20070133341
- Publication date Jun 14, 2007
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Combination nonvolatile memory using unified technology with byte,...
- Publication number 20070076480
- Publication date Apr 5, 2007
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Novel monolithic, combo nonvolatile memory allowing byte, page and...
- Publication number 20070047302
- Publication date Mar 1, 2007
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Novel monolithic, combo nonvolatile memory allowing byte, page and...
- Publication number 20060234394
- Publication date Oct 19, 2006
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Novel monolithic, combo nonvolatile memory allowing byte, page and...
- Publication number 20060176738
- Publication date Aug 10, 2006
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Novel monolithic, combo nonvolatile memory allowing byte, page and...
- Publication number 20060176739
- Publication date Aug 10, 2006
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Novel monolithic, combo nonvolatile memory allowing byte, page and...
- Publication number 20060171203
- Publication date Aug 3, 2006
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Combination nonvolatile memory using unified technology with byte,...
- Publication number 20050185501
- Publication date Aug 25, 2005
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Novel EEPROM cell structure and array architecture
- Publication number 20050169052
- Publication date Aug 4, 2005
- Aplus Flash Technology, Inc.
- Fu-Chang Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
Novel monolithic, combo nonvolatile memory allowing byte, page and...
- Publication number 20050162910
- Publication date Jul 28, 2005
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Combination nonvolatile memory using unified technology with byte,...
- Publication number 20050141298
- Publication date Jun 30, 2005
- Aplus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE

Hsing-Ya Tsao

Person

Patents Grantslast 30 patents

10T NVSRAM cell and cell operations

Low-voltage fast-write PMOS NVSRAM cell

1T1b and 2T2b flash-based, data-oriented EEPROM design

Non-boosting program inhibit scheme in NAND design

Low-voltage page buffer to be used in NVM design

On-chip HV and LV capacitors acting as the second back-up supplies...

8T NVSRAM cell and cell operations

1T1b and 2T2b flash-based, data-oriented EEPROM design

Universal timing waveforms sets to improve random access read and w...

NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash...

Row-decoder and select gate decoder structures suitable for flashed...

Apparatus and method for inhibiting excess leakage current in unsel...

Row-decoder and source-decoder structures suitable for erase in uni...

Nonvolatile memory with a unified cell structure

NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash...

Nonvolatile memory with a unified cell structure

Nonvolatile memory with a unified cell structure

Monolithic, combo nonvolatile memory allowing byte, page and block...

Combination nonvolatile memory using unified technology with byte,...

Combination nonvolatile memory using unified technology with byte,...

Monolithic, combo nonvolatile memory allowing byte, page and block...

Monolithic, combo nonvolatile memory allowing byte, page and block...

Monolithic, combo nonvolatile memory allowing byte, page and block...

Combination nonvolatile memory using unified technology with byte,...

Combination nonvolatile memory using unified technology with byte,...

Monolithic, combo nonvolatile memory allowing byte, page and block...

Monolithic, combo nonvolatile memory allowing byte, page and block...

Monolithic, combo nonvolatile memory allowing byte, page and block...

Monolithic, combo nonvolatile memory allowing byte, page and block...

Monolithic, combo nonvolatile memory allowing byte, page and block...

Patents Applicationslast 30 patents

1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN

8T NVSRAM CELL AND CELL OPERATIONS

10T NVSRAM CELL AND CELL OPERATIONS

ON-CHIP HV AND LV CAPACITORS ACTING AS THE SECOND BACK-UP SUPPLIES...

LOW-VOLTAGE FAST-WRITE PMOS NVSRAM CELL

LOW-VOLTAGE FAST-WRITE NVSRAM CELL

NON-BOOSTING PROGRAM INHIBIT SCHEME IN NAND DESIGN

Three-Dimensional Flash-Based Combo Memory and Logic Design

NEW 1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN

Low-Voltage Page Buffer to be Used in NVM Design

Universal Timing Waveforms Sets to Improve Random Access Read and W...

NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash...

NONVOLATILE MEMORY WITH A UNIFIED CELL STRUCTURE

Apparatus and method for inhibiting excess leakage current in unsel...

Row-decoder and select gate decoder structures suitable for flashed...

Row-decoder and source-decoder structures suitable for erase in uni...

NAND based NMOS NOR flash memory cell, a NAND based NMOS nor flash...

Novel monolithic, combo nonvolatile memory allowing byte, page and...

Novel monolithic, combo nonvolatile memory allowing byte, page and...

Combination nonvolatile memory using unified technology with byte,...

Combination nonvolatile memory using unified technology with byte,...

Novel monolithic, combo nonvolatile memory allowing byte, page and...

Novel monolithic, combo nonvolatile memory allowing byte, page and...

Novel monolithic, combo nonvolatile memory allowing byte, page and...

Novel monolithic, combo nonvolatile memory allowing byte, page and...

Novel monolithic, combo nonvolatile memory allowing byte, page and...

Combination nonvolatile memory using unified technology with byte,...

Novel EEPROM cell structure and array architecture

Novel monolithic, combo nonvolatile memory allowing byte, page and...

Combination nonvolatile memory using unified technology with byte,...