Hsu Kai Yang

Person

Pleasanton, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for scrubbing accumulated data errors from a m...
- Patent number 9,170,879
- Issue date Oct 27, 2015
- Headway Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for scrubbing accumulated disturb data errors...
- Patent number 8,775,865
- Issue date Jul 8, 2014
- Headway Technologies, Inc.
- Hsu Kai Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared bit line SMT MRAM array with shunting transistors between bi...
- Patent number 8,654,577
- Issue date Feb 18, 2014
- MagIC Technologies, Inc.
- Hsu-Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared bit line SMT MRAM array with shunting transistors between bi...
- Patent number 8,576,618
- Issue date Nov 5, 2013
- MagIC Technologies, Inc.
- Hsu-Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared bit line SMT MRAM array with shunting transistors between bi...
- Patent number 8,570,793
- Issue date Oct 29, 2013
- MagIC Technologies, Inc.
- Hsu-Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared bit line SMT MRAM array with shunting transistors between bi...
- Patent number 8,565,014
- Issue date Oct 22, 2013
- MagIC Technologies, Inc.
- Hsu-Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared bit line SMT MRAM array with shunting transistors between th...
- Patent number 8,437,181
- Issue date May 7, 2013
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Read disturb free SMT MRAM reference cell circuit
- Patent number 8,274,819
- Issue date Sep 25, 2012
- MagIC Technologies
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Boosted gate voltage programming for spin-torque MRAM array
- Patent number 8,248,841
- Issue date Aug 21, 2012
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Gate drive voltage boost schemes for memory array
- Patent number 8,018,758
- Issue date Sep 13, 2011
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Magnetic memory capable of minimizing gate voltage stress in unsele...
- Patent number 7,986,572
- Issue date Jul 26, 2011
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Devices using addressable magnetic tunnel junction array to detect...
- Patent number 7,977,111
- Issue date Jul 12, 2011
- MagIC Technologies, Inc.
- Xizeng Shi
- G01 - MEASURING TESTING
Information Patent Grant
Single bit line SMT MRAM array architecture and the programming method
- Patent number 7,957,183
- Issue date Jun 7, 2011
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Spin-torque MRAM: spin-RAM, array
- Patent number 7,852,662
- Issue date Dec 14, 2010
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Boosted gate voltage programming for spin-torque MRAM array
- Patent number 7,782,661
- Issue date Aug 24, 2010
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for optimizing the number of word line segments i...
- Patent number 7,613,868
- Issue date Nov 3, 2009
- Headway Technologies, Inc.
- Hsu Kai (Karl) Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and implementation of stress test for MRAM
- Patent number 7,609,543
- Issue date Oct 27, 2009
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference cell scheme for MRAM
- Patent number 7,499,314
- Issue date Mar 3, 2009
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming scheme for segmented word line MRAM array
- Patent number 7,480,172
- Issue date Jan 20, 2009
- MagIC Technologies, Inc.
- Xizeng Shi
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive algorithm for MRAM manufacturing
- Patent number 7,369,430
- Issue date May 6, 2008
- Headway Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable MRAM and method of configuration
- Patent number 7,362,644
- Issue date Apr 22, 2008
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference cell scheme for MRAM
- Patent number 7,321,507
- Issue date Jan 22, 2008
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive algorithm for MRAM manufacturing
- Patent number 7,321,519
- Issue date Jan 22, 2008
- Headway Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive algorithm for MRAM manufacturing
- Patent number 7,224,628
- Issue date May 29, 2007
- Headway Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Highly efficient segmented word line MRAM array
- Patent number 7,184,302
- Issue date Feb 27, 2007
- Headway Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
World line segment select transistor on word line current source side
- Patent number 7,180,769
- Issue date Feb 20, 2007
- Headway Technologies, Inc.
- Po-Kang Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive algorithm for MRAM manufacturing
- Patent number 7,085,183
- Issue date Aug 1, 2006
- Headway Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for providing common read and write word lines fo...
- Patent number 7,027,324
- Issue date Apr 11, 2006
- Headway Technologies, Inc.
- Hsu Kai (Karl) Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for providing a programmable current source for a...
- Patent number 6,977,838
- Issue date Dec 20, 2005
- Applied Spintronics Technology, Inc.
- David Tsang
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing electronic devices
- Patent number 6,392,427
- Issue date May 21, 2002
- Kaitech Engineering, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MASSIVELY INDEPENDENT TESTERS SYSTEM
- Publication number 20240302429
- Publication date Sep 12, 2024
- Hsu Kai YANG
- G01 - MEASURING TESTING
Information Patent Application
Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bi...
- Publication number 20130301347
- Publication date Nov 14, 2013
- Hsu-Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BI...
- Publication number 20130265821
- Publication date Oct 10, 2013
- Hsu-Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BI...
- Publication number 20130250672
- Publication date Sep 26, 2013
- International Business Machines Corporation
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bi...
- Publication number 20130250673
- Publication date Sep 26, 2013
- International Business Machines Corporation
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Shared bit line SMT MRAM array with shunting transistors between th...
- Publication number 20110317479
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for scrubbing accumulated data errors from a m...
- Publication number 20110289386
- Publication date Nov 24, 2011
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Read disturb free SMT MRAM reference cell circuit
- Publication number 20110188305
- Publication date Aug 4, 2011
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Gate drive voltage boost schemes for memory array II
- Publication number 20110038200
- Publication date Feb 17, 2011
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Gate drive voltage boost schemes for memory array
- Publication number 20110002162
- Publication date Jan 6, 2011
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for scrubbing accumulated data errors from a m...
- Publication number 20100332900
- Publication date Dec 30, 2010
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Boosted gate voltage programming for spin-torque MRAM array
- Publication number 20100321985
- Publication date Dec 23, 2010
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Read disturb-free SMT reference cell scheme
- Publication number 20100302838
- Publication date Dec 2, 2010
- MagIC Technologies, Inc.
- Pokang Wang
- G11 - INFORMATION STORAGE
Information Patent Application
Single bit line SMT MRAM array architecture and the programming method
- Publication number 20100277974
- Publication date Nov 4, 2010
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Solid state drive controller with fast NVRAM buffer and non-volatil...
- Publication number 20100191896
- Publication date Jul 29, 2010
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PC architecture using fast NV RAM in main memory
- Publication number 20100153633
- Publication date Jun 17, 2010
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Devices using addressable magnetic tunnel junction array to detect...
- Publication number 20090186770
- Publication date Jul 23, 2009
- MagIC Technologies, Inc.
- Xizeng Shi
- G01 - MEASURING TESTING
Information Patent Application
Method and implementation of stress test for MRAM
- Publication number 20090086531
- Publication date Apr 2, 2009
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Boosted gate voltage programming for spin-torque MRAM array
- Publication number 20090073756
- Publication date Mar 19, 2009
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Spin-torque MRAM: spin-RAM, array
- Publication number 20080266943
- Publication date Oct 30, 2008
- MagIC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Reference cell scheme for MRAM
- Publication number 20080094884
- Publication date Apr 24, 2008
- MaglC Technologies, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Novel programming scheme for segmented word line MRAM array
- Publication number 20070171702
- Publication date Jul 26, 2007
- MagIC Technologies, Inc. & Applied Spintronics, Inc.
- Xizeng Shi
- G11 - INFORMATION STORAGE
Information Patent Application
Configurable MRAM and method of configuration
- Publication number 20070140033
- Publication date Jun 21, 2007
- MagIC Technologies, Inc. & Applied Spintronics, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Reference cell scheme for MRAM
- Publication number 20070115717
- Publication date May 24, 2007
- MagIC Technologies, Inc. & Applied Spintronics, Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Adaptive algorithim for MRAM manufacturing
- Publication number 20060250867
- Publication date Nov 9, 2006
- HEADWAY TECHNOLOGIES, INC.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Adaptive algorithm for MRAM manufacturing
- Publication number 20060250865
- Publication date Nov 9, 2006
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Adaptive algorithm for MRAM manufacturing
- Publication number 20060250866
- Publication date Nov 9, 2006
- Headway Technologies Inc.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
WORLD LINE SEGMENT SELECT TRANSISTOR ON WORD LINE CURRENT SOURCE SIDE
- Publication number 20060227597
- Publication date Oct 12, 2006
- HEADWAY TECHNOLOGIES, INC.
- Po-Kang Wang
- G11 - INFORMATION STORAGE
Information Patent Application
Highly efficient segmented word line MRAM array
- Publication number 20060221673
- Publication date Oct 5, 2006
- HEADWAY TECHNOLOGIES, INC.
- Hsu Kai Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for optimizing the number of word line segments i...
- Publication number 20050276100
- Publication date Dec 15, 2005
- Hsu Kai (Karl) Yang
- G11 - INFORMATION STORAGE

Hsu Kai Yang

Person

Patents Grantslast 30 patents

Method and apparatus for scrubbing accumulated data errors from a m...

Method and apparatus for scrubbing accumulated disturb data errors...

Shared bit line SMT MRAM array with shunting transistors between bi...

Shared bit line SMT MRAM array with shunting transistors between bi...

Shared bit line SMT MRAM array with shunting transistors between bi...

Shared bit line SMT MRAM array with shunting transistors between bi...

Shared bit line SMT MRAM array with shunting transistors between th...

Read disturb free SMT MRAM reference cell circuit

Boosted gate voltage programming for spin-torque MRAM array

Gate drive voltage boost schemes for memory array

Magnetic memory capable of minimizing gate voltage stress in unsele...

Devices using addressable magnetic tunnel junction array to detect...

Single bit line SMT MRAM array architecture and the programming method

Spin-torque MRAM: spin-RAM, array

Boosted gate voltage programming for spin-torque MRAM array

Method and system for optimizing the number of word line segments i...

Method and implementation of stress test for MRAM

Reference cell scheme for MRAM

Programming scheme for segmented word line MRAM array

Adaptive algorithm for MRAM manufacturing

Configurable MRAM and method of configuration

Reference cell scheme for MRAM

Adaptive algorithm for MRAM manufacturing

Adaptive algorithm for MRAM manufacturing

Highly efficient segmented word line MRAM array

World line segment select transistor on word line current source side

Adaptive algorithm for MRAM manufacturing

Method and system for providing common read and write word lines fo...

Method and system for providing a programmable current source for a...

Testing electronic devices

Patents Applicationslast 30 patents

MASSIVELY INDEPENDENT TESTERS SYSTEM

Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bi...

SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BI...

SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BI...

Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bi...

Shared bit line SMT MRAM array with shunting transistors between th...

Method and apparatus for scrubbing accumulated data errors from a m...

Read disturb free SMT MRAM reference cell circuit

Gate drive voltage boost schemes for memory array II

Gate drive voltage boost schemes for memory array

Method and apparatus for scrubbing accumulated data errors from a m...

Boosted gate voltage programming for spin-torque MRAM array

Read disturb-free SMT reference cell scheme

Single bit line SMT MRAM array architecture and the programming method

Solid state drive controller with fast NVRAM buffer and non-volatil...

PC architecture using fast NV RAM in main memory

Devices using addressable magnetic tunnel junction array to detect...

Method and implementation of stress test for MRAM

Boosted gate voltage programming for spin-torque MRAM array

Spin-torque MRAM: spin-RAM, array

Reference cell scheme for MRAM

Novel programming scheme for segmented word line MRAM array

Configurable MRAM and method of configuration

Reference cell scheme for MRAM

Adaptive algorithim for MRAM manufacturing

Adaptive algorithm for MRAM manufacturing

Adaptive algorithm for MRAM manufacturing

WORLD LINE SEGMENT SELECT TRANSISTOR ON WORD LINE CURRENT SOURCE SIDE

Highly efficient segmented word line MRAM array

Method and system for optimizing the number of word line segments i...