Ihsiu Ho

Person

Salt Lake City, UT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Junction-less insulated gate current limiter device
- Patent number 9,679,890
- Issue date Jun 13, 2017
- Fairchild Semiconductor Corporation
- Tirthajyoti Sarkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming low resistance gate for power MOSFET applications
- Patent number 8,592,277
- Issue date Nov 26, 2013
- Fairchild Semiconductor Corporation
- Sreevatsa Sreekantham
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a topside contact to a backside terminal of a sem...
- Patent number 8,536,042
- Issue date Sep 17, 2013
- Fairchild Semiconductor Corporation
- John T. Andrews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D channel architecture for semiconductor devices
- Patent number 8,072,027
- Issue date Dec 6, 2011
- Fairchild Semiconductor Corporation
- Suku Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die structures for wafer-level chipscale packaging of...
- Patent number 8,058,732
- Issue date Nov 15, 2011
- Fairchild Semiconductor Corporation
- Michael D. Gruenhagen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming trenches with wide upper portion and narrow lowe...
- Patent number 8,003,522
- Issue date Aug 23, 2011
- Fairchild Semiconductor Corporation
- Hui Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for making a top-side contact to a substrate
- Patent number 7,989,884
- Issue date Aug 2, 2011
- Fairchild Semiconductor Corporation
- Chun-Tai Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of forming a topside contact to a backside ter...
- Patent number 7,884,390
- Issue date Feb 8, 2011
- Fairchild Semiconductor Corporation
- John T. Andrews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low resistance gate for power MOSFET applications and method of man...
- Patent number 7,807,536
- Issue date Oct 5, 2010
- Fairchild Semiconductor Corporation
- Sreevatsa Sreekantham
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for making a top-side contact to a substrate
- Patent number 7,482,645
- Issue date Jan 27, 2009
- Fairchild Semiconductor Corporation
- Chun-Tai Wu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
JUNCTION-LESS INSULATED GATE CURRENT LIMITER DEVICE
- Publication number 20150043114
- Publication date Feb 12, 2015
- Fairchild Semiconductor Corporation
- Tirthajyoti SARKAR
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
EDGE TERMINATION STRUCTURE FOR POWER SEMICONDUCTOR DEVICES
- Publication number 20130087852
- Publication date Apr 11, 2013
- Suku Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming a Topside Contact to a Backside Terminal of a Sem...
- Publication number 20110097894
- Publication date Apr 28, 2011
- John T. Andrews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming Low Resistance Gate for Power MOSFET Applications
- Publication number 20110014763
- Publication date Jan 20, 2011
- Sreevatsa Sreekantham
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D CHANNEL ARCHITECTURE FOR SEMICONDUCTOR DEVICES
- Publication number 20100308402
- Publication date Dec 9, 2010
- Suku Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BANDGAP ENGINEERED MOS-GATED POWER TRANSISTORS
- Publication number 20100244127
- Publication date Sep 30, 2010
- Ihsiu Ho
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Semiconductor Die Structures for Wafer-Level Chipscale Packaging of...
- Publication number 20100123225
- Publication date May 20, 2010
- Michael D. Gruenhagen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming Trenches with Wide Upper Portion and Narrow Lowe...
- Publication number 20100003823
- Publication date Jan 7, 2010
- Hui Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure for Making a Top-side Contact to a Substrate
- Publication number 20090194812
- Publication date Aug 6, 2009
- Chun-Tai Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and Method of Forming a Topside Contact to a Backside Ter...
- Publication number 20090173993
- Publication date Jul 9, 2009
- John T. Andrews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND STRUCTURE FOR MAKING A TOP-SIDE CONTACT TO A SUBSTRATE
- Publication number 20080242029
- Publication date Oct 2, 2008
- Chun-Tai Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW RESISTANCE GATE FOR POWER MOSFET APPLICATIONS AND METHOD OF MAN...
- Publication number 20070190728
- Publication date Aug 16, 2007
- Sreevatsa Sreekantham
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bandgap engineered MOS-gated power transistors
- Publication number 20060118863
- Publication date Jun 8, 2006
- Gary Dolny
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Person

Patents Grantslast 30 patents

Junction-less insulated gate current limiter device

Method of forming low resistance gate for power MOSFET applications

Method of forming a topside contact to a backside terminal of a sem...

3D channel architecture for semiconductor devices

Semiconductor die structures for wafer-level chipscale packaging of...

Method for forming trenches with wide upper portion and narrow lowe...

Structure for making a top-side contact to a substrate

Structure and method of forming a topside contact to a backside ter...

Low resistance gate for power MOSFET applications and method of man...

Method and structure for making a top-side contact to a substrate

Patents Applicationslast 30 patents

JUNCTION-LESS INSULATED GATE CURRENT LIMITER DEVICE

EDGE TERMINATION STRUCTURE FOR POWER SEMICONDUCTOR DEVICES

Method of Forming a Topside Contact to a Backside Terminal of a Sem...

Method of Forming Low Resistance Gate for Power MOSFET Applications

3D CHANNEL ARCHITECTURE FOR SEMICONDUCTOR DEVICES

BANDGAP ENGINEERED MOS-GATED POWER TRANSISTORS

Semiconductor Die Structures for Wafer-Level Chipscale Packaging of...

Method for Forming Trenches with Wide Upper Portion and Narrow Lowe...

Structure for Making a Top-side Contact to a Substrate

Structure and Method of Forming a Topside Contact to a Backside Ter...

METHOD AND STRUCTURE FOR MAKING A TOP-SIDE CONTACT TO A SUBSTRATE

LOW RESISTANCE GATE FOR POWER MOSFET APPLICATIONS AND METHOD OF MAN...

Bandgap engineered MOS-gated power transistors