LOW RESISTANCE GATE FOR POWER MOSFET APPLICATIONS AND METHOD OF MANUFACTURE

Abstract

A trench gate field effect transistor is formed as follows. A trench is formed in a semiconductor region, followed by a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench. A conductive seed layer is formed in a bottom portion of the trench over the dielectric layer. A low resistance material is grown over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1E show simplified cross section views at various stages of a manufacturing process for forming a trench gate MOSFET, in accordance with an exemplary embodiment of the invention;

FIGS. 2A-2C show simplified cross section views depicting a process sequence for forming a trenched gate using a seed layer, in accordance with an embodiment of the invention;

FIGS. 3A-3D show simplified cross section views depicting a process sequence for forming a trenched gate using a seed layer, in accordance with another embodiment of the invention;

FIGS. 4A-4C show simplified cross section views depicting a process sequence for forming a trenched gate using a seed layer, in accordance with yet another embodiment of the invention;

FIGS. 5A-5E show simplified cross section views depicting a process sequence for forming a multi-layer trenched gate structure, in accordance with an embodiment of the invention;

FIGS. 6A-6C show simplified cross section views depicting a process sequence for forming a multi-layer trenched gate structure, in accordance with another embodiment of the invention;

FIGS. 7-11 show cross section views of multi-layer trenched gate structures in accordance with embodiments of the invention; and

FIGS. 12A-12C are simplified cross section views depicting a process sequence for filling high aspect ratio contact openings, in accordance with an embodiment of the invention.

Claims

1. A method of forming a trench gate field effect transistor, comprising: forming a trench in a semiconductor region;forming a dielectric layer lining sidewalls and bottom of the trench and extending over mesa regions adjacent the trench;forming a conductive seed layer in a bottom portion of the trench over the dielectric layer; andgrowing a low resistance material over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.

2. The method of claim 1 wherein the conductive seed layer and low resistance material form at least part of a gate electrode.

3. The method of claim 1 wherein the semiconductor region comprises a substrate of a first conductivity type and a silicon region of the first conductivity type over the substrate, the silicon region having a lower doping concentration than the substrate, the method further comprising: forming a well region of a second conductivity type in the silicon region, wherein the conductive seed layer has an upper surface below a bottom surface of the well region.

4. The method of claim 1 wherein the semiconductor region comprises a substrate of a first conductivity type, the method further comprising: forming an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the epitaxial layer forming an upper part of the semiconductor region;forming a well region of a second conductivity type in the epitaxial layer; andforming source regions of the first conductivity type in the well region adjacent the trench.

5. The method of claim 1 wherein the low resistance material is grown to a height below a top surface of mesa regions adjacent the trench.

6. The method of claim 1 wherein the step of forming a conductive seed layer comprises: depositing a polysilicon layer, filling the trench; andrecessing the polysilicon layer in the trench.

7. The method of claim 6 wherein the polysilicon layer is in-situ doped to be made more conductive.

8. The method of claim 1 wherein the conductive seed layer comprises one of metal and metal compound.

9. The method of claim 1 further comprising: prior to forming the conductive seed layer, forming a thick bottom dielectric along the bottom of the trench.

10. A method of forming a shielded gate field effect transistor, comprising: forming a trench in a semiconductor region;lining lower sidewalls and bottom of the trench with shield dielectric;filling a lower portion of the trench with a shield electrode;forming an inter-electrode dielectric over the shield electrode;forming a dielectric layer lining upper trench sidewalls and extending over mesa regions adjacent the trench;forming a conductive seed layer over the inter-electrode dielectric layer; andgrowing a low resistance material over the conductive seed layer, wherein the low resistance material is selective to the conductive seed layer.

11. The method of claim 10 wherein the conductive seed layer and low resistance material form at least part of a gate electrode.

12. The method of claim 10 wherein the semiconductor region comprises a substrate of a first conductivity type and a silicon region of the first conductivity type over the substrate, the silicon region having a lower doping concentration than the substrate, the method further comprising: forming a well region of a second conductivity type in the silicon region, wherein the conductive seed layer has an upper surface below a bottom surface of the well region.

13. The method of claim 10 wherein the semiconductor region comprises a substrate of a first conductivity type, the method further comprising: forming an epitaxial layer of the first conductivity type over the substrate, the epitaxial layer having a lower doping concentration than the substrate, the epitaxial layer forming an upper part of the semiconductor region;forming a well region of a second conductivity type in the epitaxial layer; andforming source regions of the first conductivity type in the well region adjacent the trench.

14. The method of claim 10 wherein the low resistance material is grown to a height below a top surface of mesa regions adjacent the trench.

15. The method of claim 10 wherein the step of forming a conductive seed layer comprises: depositing a polysilicon layer, filling the trench; andrecessing the polysilicon layer in the trench.

16. The method of claim 15 wherein the polysilicon layer is in-situ doped to be made more conductive.

17. The method of claim 10 wherein the conductive seed layer comprises one of metal and metal compound.

18. The method of claim 10 wherein the dielectric layer is a gate dielectric layer, and the shield dielectric has a greater thickness than the gate dielectric layer.

19-140. (canceled)