Patent Application
20130087852
This application relates generally to semiconductor devices and methods for making such devices. More specifically, this application describes edge termination structures for power semiconductor devices and methods for making such structures.
Semiconductor devices containing integrated circuits (ICs) or discrete devices are used in a wide variety of electronic apparatus. The IC devices (or chips, or discrete devices) comprise a miniaturized electronic circuit that has been manufactured in the surface of a substrate of semiconductor material. The circuits are composed of many overlapping layers, including layers containing dopants that can be diffused into the substrate (called diffusion layers) or ions that are implanted (implant layers) into the substrate. Other layers are conductors (polysilicon or metal layers) or connections between the conducting layers (via or contact layers). IC devices or discrete devices can be fabricated in a layer-by-layer process that uses a combination of many steps, including growing layers, imaging, deposition, etching, doping and cleaning Silicon wafers are typically used as the substrate and photolithography is used to mark different areas of the substrate to be doped or to deposit and define polysilicon, insulators, or metal layers.
Power semiconductor devices are often used as switches or rectifiers in electronic circuits. When connected to a circuit board, they can be used in a wide variety of apparatus including automotive electronics, disk drives and power supplies. Some power semiconductor devices can be formed in a trench that has been created in a substrate. One feature making the trench configuration attractive is that the current flows vertically through the channel of the devices in the trench. This permits a higher cell and/or current channel densities than other semiconductor devices where the current flows horizontally through the channel and then vertically through the drain. Greater cell and/or current channel densities generally mean more devices and/or current channels can be manufactured per unit area of the substrate, thereby increasing the current density of the power semiconductor device.
This application describes edge termination structures for power semiconductor devices and methods for making such structures. The power semiconductor devices (or power devices) contain a substrate with an epitaxial layer thereon, an array of substantially-parallel, active trenches formed in the epitaxial layer, with the active trenches containing a transistor structure with an insulated gate conducting layer, a superjunction or shielded region adjacent the active trenches; a peripheral trench surrounding the active trenches, and a source contact area within an upper surface of the epitaxial layer, where the gate conducting layer extends over the superjunction or shielded region and over the surrounding peripheral trench. Such a configuration allows the edge termination structure to be used with a wide range of breakdown voltages in power MOSFET devices containing PN superjunction structures.
The following description can be better understood in light of the Figures, in which:
The Figures illustrate specific aspects of the semiconductor devices and methods for making such devices. Together with the following description, the Figures demonstrate and explain the principles of the methods and structures produced through these methods. In the drawings, the thickness of layers and regions are exaggerated for clarity. The same reference numerals in different drawings represent the same element, and thus their descriptions will not be repeated. As the terms on, attached to, or coupled to are used herein, one object (e.g., a material, a layer, a substrate, etc.) can be on, attached to, or coupled to another object regardless of whether the one object is directly on, attached, or coupled to the other object or there are one or more intervening objects between the one object and the other object. Also, directions (e.g., above, below, top, bottom, side, up, down, under, over, upper, lower, horizontal, vertical, “x,” “y,” “z,” etc.), if provided, are relative and provided solely by way of example and for ease of illustration and discussion and not by way of limitation. In addition, where reference is made to a list of elements (e.g., elements a, b, c), such reference is intended to include any one of the listed elements by itself, any combination of less than all of the listed elements, and/or a combination of all of the listed elements.
The following description supplies specific details in order to provide a thorough understanding. Nevertheless, the skilled artisan would understand that the semiconductor devices and associated methods of making and using the devices can be implemented and used without employing these specific details. Indeed, the semiconductor devices and associated methods can be placed into practice by modifying the illustrated devices and methods and can be used in conjunction with any other apparatus and techniques conventionally used in the industry. For example, while description refers to trench MOSFET devices, it could be modified for other semiconductor devices formed in trenches, such as Static Induction Transistor (SIT) devices, Static Induction Thyristor (SITh) devices, IGBT devices, BJT devices, BSIT devices, JFET devices, and thyristor devices.
Some embodiments of the edge termination structures for power semiconductor devices and methods for making such structures are shown in
The methods begin in some embodiments, as depicted in
In some embodiments, the substrate 105 contains one or more epitaxial (“epi”) Si layers (individually or collectively depicted as epitaxial layer 110) located on an upper surface thereof. For example, a lightly doped p-epi layer can exist between substrate 105 and epitaxial layer 110. The epitaxial layer(s) 110 can be provided using any known process in the art, including any known epitaxial deposition process. The epitaxial layer(s) can be lightly doped with a p-type dopant.
Next, as shown in
The epitaxial layer 110 can then be etched by any known process until the first trench 120 has reached the desired depth and width in the epitaxial layer 110 (or substrate 105). The depth and width of the trench 120, as well as the aspect ratio of the width to the depth, can be controlled so that so a later deposited oxide layer properly fills in the trench and avoids the formation of voids. In some embodiments, the depth of the first trench structure 120 can range from about 0.1 to about 100 μm and the width can range from about 0.1 to about 50 μm. With such depths and widths, the aspect ratio of the trench can range from about 1:1 to about 1:50.
In some embodiments, a second trench structure 122 (or peripheral trench) can be formed at the same time at the first trench structure 120. In some configurations, the depth of the second trench structure 122 can be substantially the same as the depth of the first trench structure 120. In other configurations, the depth of the second trench structure 122 can be greater than the depth of the first trench structure 120. In some embodiments, the depth of the second trench structure 122 can be greater than the depth of the first trench structure up to about 100%. In other embodiments, the depth of the second trench structure 122 can be greater than the depth of the first trench structure by up to about 5%.
In some embodiments, the sidewalls of the trenches 120/122 are not perpendicular to the upper surface of the epitaxial layer 110. Instead, the angles of the trench sidewall can range from about 90 degrees (a vertical sidewall) to about 60 degrees relative to the upper surface of the epitaxial layer 110. The trench angle can be controlled so a later deposited oxide layer or any other material properly fills in the trench and avoids the formation of voids.
In some embodiments, as shown in
The mask 115 can be removed using any process known in the art. Then, as shown in
After the oxide layer 130 has been deposited, an etchback process can be used to remove the excess oxide material above and in the first trenches 120. After the etchback process, an oxide region 140 is formed in the bottom of the first trench 120, as shown in
With the second trench structures 122, however, no removal process for the oxide layer 130 is performed. Rather, the oxide layer 130 remains in and above the second trenches 122, as shown in
After formation of the bottom oxide region 140 in first trenches 120, a gate insulating layer (such as a gate oxide layer 133) can be grown on the exposed sidewalls of the trench 120 that are not covered by the bottom oxide layer 140, as shown in
Subsequently, a conductive layer can be deposited in the middle or upper part of the trenches 120 and on the bottom oxide region 140. The conductive layer can comprise any conductive and/or semiconductive material known in the art including any metal, silicide, semiconducting material, doped polysilicon, or combinations thereof. This conductive layer can be deposited by any known deposition process, including chemical vapor deposition processes (CVD, PECVD, LPCVD, etc.) or sputtering processes using the desired metal as the sputtering target. In some configurations, the conductive layer extends over part of the oxide layer 132 above the second trenches 122, as explained in more detail below.
The conductive layer can be deposited so that it fills and overflows over the upper part of the first trenches 120. Then, a gate 150 (or gate conductor) can be formed from the conductive layer using any process known in the art. In some embodiments, the gate 150 can be formed by removing the upper portion of the conductive layer using any process known the art, including any etchback process. The result of the removal process leaves a conductive layer (the gate 150) overlying the first oxide region 140 in the trench 120 and sandwiched between the gate oxide layers 133, as shown in
Then, a p-type dopant region 145 can be formed in an upper portion of the epitaxial layer 110, as shown in
The remainder of the transistor (i.e., MOSFET) structure can then be formed in the first trenches 120 using any processing known in the art. No MOSFET structure is formed in the second trenches 122. In some embodiments, the MOSFET structure can be completed by forming contact regions on the exposed upper surface of the epitaxial layer 110. Then, the upper surface of the gate is covered with an overlying insulating layer and used to form an insulation cap. Then, the contact region and the p-dopant region 145 can be etched to form an insert region. A source layer (or region) can then be deposited over the upper portions of the insulation cap and the contact region. And after (or before) the source layer has been formed, a drain can be formed on the backside of the substrate using any process known in the art.
These methods can form the semiconductor structures 200 shown in
A cross-section of the semiconductor structure 200 along line A of
The semiconductor structure 200 contains multiple second (peripheral) trenches 122 filled with insulating layer 132. In some configurations, the peripheral trenches 122 can contain a dielectric material, an insulator, a semi-insulator, a conductor, or a combination thereof.
The number of peripheral trenches 122 in the semiconductor structure 200 depends on the voltage ratings and the required leakage performance of the device. In some embodiments, the number of second trenches 122 can range up to 50. In other embodiments, the number of second trenches 122 ranges from 1 to 10. In yet other embodiments, the number of second trenches 122 is about 5. When more than one perimeter trench 122 is used, the voltage can be spread out laterally.
A cross-section of the semiconductor structure 200 along line B of
As shown in
The semiconductor structure 200 also contains a transition point (shown by line C) and source contact area (shown by line D). The transition point is that location in the structure at which the gate conducting line 150 extends above the mesa surface and continues over the second, perimeter trench 122 so it can be connected to the gate bus (not shown). A top view of the transition point (line C) is depicted in
As shown in both
These methods of manufacturing and the devices formed have several useful features. The semiconductor devices described in the U.S. patent applications detailed above contain PN superjunctions in MOSFET, SIT, and JFET devices, as described therein. The edge termination designs described herein can be used with numerous SIT, JFET, and MOSFET architectures that contain superjunction structures, shielded structures, and various reduced surface field (resurf) structures. Further, the termination designs described herein can be used in a wide range of breakdown voltage ratings (low to high voltage) with only one design (and only one method needed to make that design).
The termination methods described above can also reduce the non-active area of the conventional termination regions used for superjunction devices. P/N superjunction MOSFET devices typically require termination regions that contain multiple P and N rings in the peripheral region. But such a configuration consumes significant area in the non-active region.
The description above describes using the termination structures and methods in a vertical channel MOSFET. In other configurations, though, the termination structures and methods can be used in a planar channel MOSFET device, similar to the vertical channel MOSFET case except that the gate structure can be made on the mesa surface as shown in
In some embodiments, the application relates to methods for making a semiconductor structures comprising: providing a semiconductor substrate with an epitaxial layer thereon; providing an array of substantially-parallel, active trenches formed in the epitaxial layer, where the trenches contain a transistor structure with an insulated gate conducting layer; providing a superjunction or shielded region adjacent the active trenches; providing a peripheral trench surrounding the active trenches; and providing a source contact area within an upper surface of the epitaxial layer; where the gate conducting layer extends over the superjunction or shielded region and over the surrounding peripheral trench.
In some embodiments, the application relates to methods for making a semiconductor structures comprising: forming an epitaxial layer on a semiconductor substrate; etching an array of substantially-parallel, active trenches in the epitaxial layer; forming a transistor structure with an insulated gate conducting layer in the active trenches; providing a superjunction, shielded region, or resurf structures adjacent the active trenches; etching a peripheral trench to surround the active trenches; and doping an upper surface of the epitaxial layer to provide a source contact area; where the gate conducting layer extends over the superjunction or shielded region and over the surrounding peripheral trench.
In addition to any previously indicated modification, numerous other variations and alternative arrangements may be devised by those skilled in the art without departing from the spirit and scope of this description, and appended claims are intended to cover such modifications and arrangements. Thus, while the information has been described above with particularity and detail in connection with what is presently deemed to be the most practical and preferred aspects, it will be apparent to those of ordinary skill in the art that numerous modifications, including, but not limited to, form, function, manner of operation and use may be made without departing from the principles and concepts set forth herein. Also, as used herein, examples are meant to be illustrative only and should not be construed to be limiting in any manner.
