Irving Memis

Person

Vestal, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-layer embedded capacitance and resistance substrate core
- Patent number 8,144,480
- Issue date Mar 27, 2012
- Endicott Interconnect Technologies, Inc.
- Rabindra N. Das
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High performance chip carrier substrate
- Patent number 7,886,435
- Issue date Feb 15, 2011
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High performance chip carrier substrate
- Patent number 7,863,526
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi-layer embedded capacitance and resistance substrate core
- Patent number 7,791,897
- Issue date Sep 7, 2010
- Endicott Interconnect Technologies, Inc.
- Rabindra N. Das
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of making multi-chip electronic package with reduced line skew
- Patent number 7,622,384
- Issue date Nov 24, 2009
- Endicott Interconnect Technologies, Inc.
- Irving Memis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of making circuitized substrate with improved impedance cont...
- Patent number 7,589,283
- Issue date Sep 15, 2009
- Endicott Interconnect Technologies, Inc.
- Charles E. Danoski
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low moisture absorptive circuitized substrate with reduced thermal...
- Patent number 7,470,990
- Issue date Dec 30, 2008
- Endicott Interconnect Technologies, Inc.
- Robert M. Japp
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High performance chip carrier substrate
- Patent number 7,454,833
- Issue date Nov 25, 2008
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of making same low moisture absorptive circuitized substrave...
- Patent number 7,416,972
- Issue date Aug 26, 2008
- Endicott Interconnect Technologies, Inc.
- Robert M. Japp
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi-chip electronic package with reduced line skew and circuitize...
- Patent number 7,332,818
- Issue date Feb 19, 2008
- Endicott Interconnect Technologies, Inc.
- Irving Memis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Circuitized substrate with improved impedance control circuitry, me...
- Patent number 7,294,791
- Issue date Nov 13, 2007
- Endicott Interconnect Technologies, Inc.
- Charles E. Danoski
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High wireability microvia substrate
- Patent number 7,279,798
- Issue date Oct 9, 2007
- International Business Machines Corporation
- Irving Memis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High performance chip carrier substrate
- Patent number 7,214,886
- Issue date May 8, 2007
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low moisture absorptive circuitized substrate, method of making sam...
- Patent number 7,145,221
- Issue date Dec 5, 2006
- Endicott Interconnect Technologies, Inc.
- Irving Memis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Extension of fatigue life for C4 solder ball to chip connection
- Patent number 7,119,003
- Issue date Oct 10, 2006
- International Business Machines Corporation
- William E. Bernier
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Extension of fatigue life for C4 solder ball to chip connection
- Patent number 7,067,916
- Issue date Jun 27, 2006
- International Business Machines Corporation
- William E. Bernier
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High wireability microvia substrate
- Patent number 6,965,170
- Issue date Nov 15, 2005
- International Business Machines Corporation
- Irving Memis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High density microvia substrate with high wireability
- Patent number 6,919,635
- Issue date Jul 19, 2005
- International Business Machines Corporation
- Kazushige Kawasaki
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Full additive process with filled plated through holes
- Patent number 6,664,485
- Issue date Dec 16, 2003
- International Business Machines Corporation
- Anilkumar C. Bhatt
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Selective C4 connection in IC packaging
- Patent number 6,650,016
- Issue date Nov 18, 2003
- International Business Machines Corporation
- Stephen W. MacQuarrie
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Full additive process with filled plated through holes
- Patent number 6,418,616
- Issue date Jul 16, 2002
- International Business Machines Corporation
- Anilkumar C. Bhatt
- B32 - LAYERED PRODUCTS
Information Patent Grant
Process for manufacturing a multi-layer circuit board
- Patent number 6,391,210
- Issue date May 21, 2002
- International Business Machines Corporation
- Bernd K. Appelt
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Process for design and manufacture of fine line circuits on planari...
- Patent number 6,290,860
- Issue date Sep 18, 2001
- International Business Machines Corporation
- Bernd K. Appelt
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Attaching heat sinks directly to flip chips and ceramic chip carriers
- Patent number 6,251,707
- Issue date Jun 26, 2001
- International Business Machines Corporation
- William Emmett Bernier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Full additive process with filled plated through holes
- Patent number 6,195,883
- Issue date Mar 6, 2001
- International Business Machines Corporation
- Anilkumar C. Bhatt
- B32 - LAYERED PRODUCTS
Information Patent Grant
Circuit board with primary and secondary through holes
- Patent number 6,162,997
- Issue date Dec 19, 2000
- International Business Machines Corporation
- Irving Memis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Attaching heat sinks directly to flip chips and ceramic chip carriers
- Patent number 6,069,023
- Issue date May 30, 2000
- International Business Machines Corporation
- William Emmett Bernier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Printed circuit boards for mounting a semiconductor integrated circ...
- Patent number 5,965,944
- Issue date Oct 12, 1999
- International Business Machines Corporation
- Edward Jay Frankoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Attaching heat sinks directly to flip chips and ceramic chip carriers
- Patent number 5,847,929
- Issue date Dec 8, 1998
- International Business Machines Corporation
- William Emmett Bernier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving the adhesion of polymeric adhesives to nickel...
- Patent number 5,532,024
- Issue date Jul 2, 1996
- International Business Machines Corporation
- Steven F. Arndt
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Patents Applicationslast 30 patents

Information Patent Application
MULTI-LAYER EMBEDDED CAPACITANCE AND RESISTANCE SUBSTRATE CORE
- Publication number 20100167210
- Publication date Jul 1, 2010
- Endicott Interconnect Technologies, Inc.
- Rabindra N. Das
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Mulit-layer embedded capacitance and resistance substrate core
- Publication number 20100060381
- Publication date Mar 11, 2010
- Endicott Interconnect Technologies, Inc.
- Rabindra N. Das
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
HIGH PERFORMANCE CHIP CARRIER SUBSTRATE
- Publication number 20080308923
- Publication date Dec 18, 2008
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
HIGH PERFORMANCE CHIP CARRIER SUBSTRATE
- Publication number 20080296054
- Publication date Dec 4, 2008
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method of making multi-chip electronic package with reduced line skew
- Publication number 20080102562
- Publication date May 1, 2008
- Endicott Interconnect Tehnologies, Inc.
- Irving Memis
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Method of making circuitized substrate with improved impedance cont...
- Publication number 20070284140
- Publication date Dec 13, 2007
- Endicott Interconnect Technologies, Inc.
- Charles E. Danoski
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method of making same low moisture absorptive circuitized substrave...
- Publication number 20070182016
- Publication date Aug 9, 2007
- Endicott Interconnect Technologies, Inc.
- Robert M. Japp
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
High performance chip carrier substrate
- Publication number 20070175658
- Publication date Aug 2, 2007
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Multi-chip electronic package with reduced line skew, method of mak...
- Publication number 20060255460
- Publication date Nov 16, 2006
- Endicott Interconnect Technologies, Inc.
- Irving Memis
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Circuitized substrate with improved impedance contol circuitry, met...
- Publication number 20060065433
- Publication date Mar 30, 2006
- Endicott Interconnect Technologies, Inc.
- Charles E. Danoski
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
High wireability microvia substrate
- Publication number 20060012054
- Publication date Jan 19, 2006
- International Business Machines Corporation
- Irving Memis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Low moisture absorptive circuitized substrate, method of making sam...
- Publication number 20050224251
- Publication date Oct 13, 2005
- Endicott Interconnect Technologies, Inc.
- Irving Memis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Extension of fatigue life for C4 solder ball to chip connection
- Publication number 20050224973
- Publication date Oct 13, 2005
- William E. Bernier
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Low moisture absorptive circuitized substrate with reduced thermal...
- Publication number 20050218524
- Publication date Oct 6, 2005
- Endicott Interconnect Technologies, Inc.
- Robert M. Japp
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
High performance chip carrier substrate
- Publication number 20050109535
- Publication date May 26, 2005
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
High wireability microvia substrate
- Publication number 20050104221
- Publication date May 19, 2005
- International Business Machines Corporation
- Irving Memis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
HIGH DENSITY MICROVIA SUBSTRATE WITH HIGH WIREABILITY
- Publication number 20050093133
- Publication date May 5, 2005
- International Business Machines Corporation
- Kazushige Kawasaki
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Extension of fatigue life for C4 solder ball to chip connection
- Publication number 20020195707
- Publication date Dec 26, 2002
- International Business Machines Corporation
- William E. Bernier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for manufacturing a multi-layer circuit board
- Publication number 20010042733
- Publication date Nov 22, 2001
- Bernd K. Appelt
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Full additive process with filled plated through holes
- Publication number 20010009066
- Publication date Jul 26, 2001
- International Business Machines Corporation
- Anilkumar C. Bhatt
- B32 - LAYERED PRODUCTS
Information Patent Application
Full additive process with filled plated through holes
- Publication number 20010007289
- Publication date Jul 12, 2001
- International Business Machines Corporation
- Anilkumar C. Bhatt
- B32 - LAYERED PRODUCTS

Irving Memis

Person

Patents Grantslast 30 patents

Multi-layer embedded capacitance and resistance substrate core

High performance chip carrier substrate

High performance chip carrier substrate

Multi-layer embedded capacitance and resistance substrate core

Method of making multi-chip electronic package with reduced line skew

Method of making circuitized substrate with improved impedance cont...

Low moisture absorptive circuitized substrate with reduced thermal...

High performance chip carrier substrate

Method of making same low moisture absorptive circuitized substrave...

Multi-chip electronic package with reduced line skew and circuitize...

Circuitized substrate with improved impedance control circuitry, me...

High wireability microvia substrate

High performance chip carrier substrate

Low moisture absorptive circuitized substrate, method of making sam...

Extension of fatigue life for C4 solder ball to chip connection

Extension of fatigue life for C4 solder ball to chip connection

High wireability microvia substrate

High density microvia substrate with high wireability

Full additive process with filled plated through holes

Selective C4 connection in IC packaging

Full additive process with filled plated through holes

Process for manufacturing a multi-layer circuit board

Process for design and manufacture of fine line circuits on planari...

Attaching heat sinks directly to flip chips and ceramic chip carriers

Full additive process with filled plated through holes

Circuit board with primary and secondary through holes

Attaching heat sinks directly to flip chips and ceramic chip carriers

Printed circuit boards for mounting a semiconductor integrated circ...

Attaching heat sinks directly to flip chips and ceramic chip carriers

Method for improving the adhesion of polymeric adhesives to nickel...

Patents Applicationslast 30 patents

MULTI-LAYER EMBEDDED CAPACITANCE AND RESISTANCE SUBSTRATE CORE

Mulit-layer embedded capacitance and resistance substrate core

HIGH PERFORMANCE CHIP CARRIER SUBSTRATE

HIGH PERFORMANCE CHIP CARRIER SUBSTRATE

Method of making multi-chip electronic package with reduced line skew

Method of making circuitized substrate with improved impedance cont...

Method of making same low moisture absorptive circuitized substrave...

High performance chip carrier substrate

Multi-chip electronic package with reduced line skew, method of mak...

Circuitized substrate with improved impedance contol circuitry, met...

High wireability microvia substrate

Low moisture absorptive circuitized substrate, method of making sam...

Extension of fatigue life for C4 solder ball to chip connection

Low moisture absorptive circuitized substrate with reduced thermal...

High performance chip carrier substrate

High wireability microvia substrate

HIGH DENSITY MICROVIA SUBSTRATE WITH HIGH WIREABILITY

Extension of fatigue life for C4 solder ball to chip connection

Process for manufacturing a multi-layer circuit board

Full additive process with filled plated through holes

Full additive process with filled plated through holes