Iulian Constantin Gradinariu

Person

Colorado Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low standby power with fast turn on method for non-volatile memory...
- Patent number 12,014,800
- Issue date Jun 18, 2024
- LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Cristinel Zonte
- G11 - INFORMATION STORAGE
Information Patent Grant
Closed loop oscillator
- Patent number 11,990,907
- Issue date May 21, 2024
- Cypress Semiconductor Corporation
- Nandakishore Raimar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low standby power with fast turn on method for non-volatile memory...
- Patent number 10,998,019
- Issue date May 4, 2021
- Longitude Flash Memory Solutions, Ltd.
- Cristinel Zonte
- G11 - INFORMATION STORAGE
Information Patent Grant
Low standby power with fast turn on method for non-volatile memory...
- Patent number 10,510,387
- Issue date Dec 17, 2019
- LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Cristinel Zonte
- G11 - INFORMATION STORAGE
Information Patent Grant
Low inrush circuit for power up and deep power down exit
- Patent number 10,254,812
- Issue date Apr 9, 2019
- Cypress Semiconductor Corporation
- Mohandas Sivadasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low standby power with fast turn on for non-volatile memory devices
- Patent number 10,062,423
- Issue date Aug 28, 2018
- Cypress Semiconductor Corporation
- Cristinel Zonte
- G11 - INFORMATION STORAGE
Information Patent Grant
Biasing circuit for level shifter with isolation
- Patent number 9,866,216
- Issue date Jan 9, 2018
- Cypress Semiconductor Corporation
- Iulian C. Gradinariu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Differential sigma-delta capacitance sensing devices and methods
- Patent number 9,639,226
- Issue date May 2, 2017
- Cypress Semiconductor Corporation
- Iulian C. Gradinariu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low standby power with fast turn on for non-volatile memory devices
- Patent number 9,449,655
- Issue date Sep 20, 2016
- Cypress Semiconductor Corporation
- Cristinel Zonte
- G11 - INFORMATION STORAGE
Information Patent Grant
Biasing circuit for level shifter with isolation
- Patent number 9,438,240
- Issue date Sep 6, 2016
- Cypress Semiconductor Corporation
- Iulian C. Gradinariu
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage-mode band-gap reference circuit with temperature drift and...
- Patent number 8,791,683
- Issue date Jul 29, 2014
- Linear Technology Corporation
- Edson Wayne Porter
- G05 - CONTROLLING REGULATING
Information Patent Grant
Substrate bias feedback scheme to reduce chip leakage power
- Patent number 8,587,365
- Issue date Nov 19, 2013
- Cypress Semiconductor Corporation
- Vijay Kumar Srinivasa Raghavan
- G05 - CONTROLLING REGULATING
Information Patent Grant
Substrate bias feedback scheme to reduce chip leakage power
- Patent number 8,283,972
- Issue date Oct 9, 2012
- Cypress Semiconductor Corporation
- Vijay Kumar Srinivasa Raghavan
- G05 - CONTROLLING REGULATING
Information Patent Grant
Substrate bias feedback scheme to reduce chip leakage power
- Patent number 8,085,085
- Issue date Dec 27, 2011
- Cypress Semiconductor Corporation
- Vijay Kumar Srinivasa Raghavan
- G05 - CONTROLLING REGULATING
Information Patent Grant
Substrate bias feedback scheme to reduce chip leakage power
- Patent number 7,746,160
- Issue date Jun 29, 2010
- Cypress Semiconductor Corporation
- Vijay Kumar Srinivasa Raghavan
- G05 - CONTROLLING REGULATING
Information Patent Grant
Low power Bandgap reference circuit with increased accuracy and red...
- Patent number 7,683,701
- Issue date Mar 23, 2010
- Cypress Semiconductor Corporation
- Bogdan I. Georgescu
- G05 - CONTROLLING REGULATING
Information Patent Grant
Substrate bias feedback scheme to reduce chip leakage power
- Patent number 7,504,876
- Issue date Mar 17, 2009
- Cypress Semiconductor Corporation
- Vijay Kumar Srinivasa Raghavan
- G05 - CONTROLLING REGULATING
Information Patent Grant
Shunt type voltage regulator
- Patent number 7,262,586
- Issue date Aug 28, 2007
- Cypress Semiconductor Corporation
- Iulian Gradinariu
- G05 - CONTROLLING REGULATING
Information Patent Grant
Architecture, method(s) and circuitry for low power memories
- Patent number 6,674,682
- Issue date Jan 6, 2004
- Cypress Semiconductor Corp.
- Keith A. Ford
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel test in asynchronous memory with single-ended output path
- Patent number 6,662,315
- Issue date Dec 9, 2003
- Cypress Semiconductor Corporation
- Iulian C. Gradinariu
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture, circuitry and method of transferring data into and/or...
- Patent number 6,629,185
- Issue date Sep 30, 2003
- Cypress Semiconductor Corp.
- John Silver
- G11 - INFORMATION STORAGE
Information Patent Grant
Block redundancy in ultra low power memory circuits
- Patent number 6,535,437
- Issue date Mar 18, 2003
- Cypress Semiconductor Corp.
- John J. Silver
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel test in asynchronous memory with single-ended output path
- Patent number 6,530,040
- Issue date Mar 4, 2003
- Cypress Semiconductor Corp.
- Iulian C. Gradinariu
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture, method (s) and circuitry for low power memories
- Patent number 6,493,283
- Issue date Dec 10, 2002
- Cypress Semiconductor Corp.
- Keith A. Ford
- G11 - INFORMATION STORAGE
Information Patent Grant
Output data path scheme in a memory device
- Patent number 6,378,008
- Issue date Apr 23, 2002
- Cypress Semiconductor Corporation
- Iulian C. Gradinariu
- G11 - INFORMATION STORAGE
Information Patent Grant
Scheme for reducing leakage current in an input buffer
- Patent number 6,323,701
- Issue date Nov 27, 2001
- Cypress Semiconductor Corporation
- Iulian C. Gradinariu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture, method(s) and circuitry for low power memories
- Patent number 6,163,495
- Issue date Dec 19, 2000
- Cypress Semiconductor Corp.
- Keith A. Ford
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory with interdigitated array having bit line pair...
- Patent number 6,118,727
- Issue date Sep 12, 2000
- Cypress Semiconductor Corporation
- James D. Allan
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell sensing method and circuitry for bit line equalization
- Patent number 5,828,614
- Issue date Oct 27, 1998
- Cypress Semiconductor Corp.
- Iulian Gradinariu
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CLOSED LOOP OSCILLATOR
- Publication number 20240106422
- Publication date Mar 28, 2024
- CYPRESS SEMICONDUCTOR CORPORATION
- Nandakishore RAIMAR
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW STANDBY POWER WITH FAST TURN ON METHOD FOR NON-VOLATILE MEMORY...
- Publication number 20230197128
- Publication date Jun 22, 2023
- LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Cristinel Zonte
- G11 - INFORMATION STORAGE
Information Patent Application
LOW STANDBY POWER WITH FAST TURN ON METHOD FOR NON-VOLATILE MEMORY...
- Publication number 20210327477
- Publication date Oct 21, 2021
- LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Cristinel Zonte
- G11 - INFORMATION STORAGE
Information Patent Application
LOW STANDBY POWER WITH FAST TURN ON METHOD FOR NON-VOLATILE MEMORY...
- Publication number 20200234746
- Publication date Jul 23, 2020
- LONGITUDE FLASH MEMORY SOLUTIONS LTD.
- Cristinel Zonte
- G11 - INFORMATION STORAGE
Information Patent Application
LOW STANDBY POWER WITH FAST TURN ON METHOD FOR NON-VOLATILE MEMORY...
- Publication number 20190080732
- Publication date Mar 14, 2019
- CYPRESS SEMICONDUCTOR CORPORATION
- Cristinel Zonte
- G11 - INFORMATION STORAGE
Information Patent Application
LOW STANDBY POWER WITH FAST TURN ON FOR NON-VOLATILE MEMORY DEVICES
- Publication number 20170098468
- Publication date Apr 6, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Cristinel Zonte
- G11 - INFORMATION STORAGE
Information Patent Application
DIFFERENTIAL SIGMA-DELTA CAPACITANCE SENSING DEVICES AND METHODS
- Publication number 20170060297
- Publication date Mar 2, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Iulian C. Gradinariu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERPOLATING DIGITAL-TO-ANALOG CONVERTER WITH SEPARATE BIAS CURREN...
- Publication number 20120206284
- Publication date Aug 16, 2012
- Linear Technology Corporation
- Iulian Constantin Gradinariu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low power bandgap reference circuit with increased accuracy and red...
- Publication number 20070152740
- Publication date Jul 5, 2007
- Bogdan I. Georgescu
- G05 - CONTROLLING REGULATING
Information Patent Application
Architecture, method(s) and circuitry for low power memories
- Publication number 20020191470
- Publication date Dec 19, 2002
- Keith A. Ford
- G11 - INFORMATION STORAGE

Iulian Constantin Gradinariu

Person

Patents Grantslast 30 patents

Low standby power with fast turn on method for non-volatile memory...

Closed loop oscillator

Low standby power with fast turn on method for non-volatile memory...

Low standby power with fast turn on method for non-volatile memory...

Low inrush circuit for power up and deep power down exit

Low standby power with fast turn on for non-volatile memory devices

Biasing circuit for level shifter with isolation

Differential sigma-delta capacitance sensing devices and methods

Low standby power with fast turn on for non-volatile memory devices

Biasing circuit for level shifter with isolation

Voltage-mode band-gap reference circuit with temperature drift and...

Substrate bias feedback scheme to reduce chip leakage power

Substrate bias feedback scheme to reduce chip leakage power

Substrate bias feedback scheme to reduce chip leakage power

Substrate bias feedback scheme to reduce chip leakage power

Low power Bandgap reference circuit with increased accuracy and red...

Substrate bias feedback scheme to reduce chip leakage power

Shunt type voltage regulator

Architecture, method(s) and circuitry for low power memories

Parallel test in asynchronous memory with single-ended output path

Architecture, circuitry and method of transferring data into and/or...

Block redundancy in ultra low power memory circuits

Parallel test in asynchronous memory with single-ended output path

Architecture, method (s) and circuitry for low power memories

Output data path scheme in a memory device

Scheme for reducing leakage current in an input buffer

Architecture, method(s) and circuitry for low power memories

Semiconductor memory with interdigitated array having bit line pair...

Memory cell sensing method and circuitry for bit line equalization

Patents Applicationslast 30 patents

CLOSED LOOP OSCILLATOR

LOW STANDBY POWER WITH FAST TURN ON METHOD FOR NON-VOLATILE MEMORY...

LOW STANDBY POWER WITH FAST TURN ON METHOD FOR NON-VOLATILE MEMORY...

LOW STANDBY POWER WITH FAST TURN ON METHOD FOR NON-VOLATILE MEMORY...

LOW STANDBY POWER WITH FAST TURN ON METHOD FOR NON-VOLATILE MEMORY...

LOW STANDBY POWER WITH FAST TURN ON FOR NON-VOLATILE MEMORY DEVICES

DIFFERENTIAL SIGMA-DELTA CAPACITANCE SENSING DEVICES AND METHODS

INTERPOLATING DIGITAL-TO-ANALOG CONVERTER WITH SEPARATE BIAS CURREN...

Low power bandgap reference circuit with increased accuracy and red...

Architecture, method(s) and circuitry for low power memories