Ivan Pavisic

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Architectural floorplan for a structured ASIC manufactured on a 28...
- Patent number 9,024,657
- Issue date May 5, 2015
- eASIC Corporation
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and computer program for generating grounded shielding wires...
- Patent number 8,516,425
- Issue date Aug 20, 2013
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for balancing signal delay skew
- Patent number 8,239,813
- Issue date Aug 7, 2012
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal delay skew reduction system
- Patent number 7,996,804
- Issue date Aug 9, 2011
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Density driven layout for RRAM configuration module
- Patent number 7,818,703
- Issue date Oct 19, 2010
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for fast unbalanced pipeline architecture
- Patent number 7,667,494
- Issue date Feb 23, 2010
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built in self test transport controller architecture
- Patent number 7,546,505
- Issue date Jun 9, 2009
- LSI Corporation
- Sergey Gribok
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimizing IC clock structures by minimizing clock uncertainty
- Patent number 7,356,785
- Issue date Apr 8, 2008
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for avoiding false path pessimism in estimating net delay fo...
- Patent number 7,334,204
- Issue date Feb 19, 2008
- LSI Logic Corporation
- Weiqing Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Density driven layout for RRAM configuration module
- Patent number 7,246,337
- Issue date Jul 17, 2007
- LSI Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of buffer insertion to achieve pin specific delays
- Patent number 7,243,324
- Issue date Jul 10, 2007
- LSI Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory tiling architecture
- Patent number 7,207,026
- Issue date Apr 17, 2007
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compact custom layout for RRAM column controller
- Patent number 7,194,717
- Issue date Mar 20, 2007
- LSI Logic Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing IC clock structures by minimizing clock uncertainty
- Patent number 7,096,442
- Issue date Aug 22, 2006
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for classifying an integrated circuit for optical...
- Patent number 7,093,228
- Issue date Aug 15, 2006
- LSI Logic Corporation
- Alexandre Andreev
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
RRAM backend flow
- Patent number 7,028,274
- Issue date Apr 11, 2006
- LSI Logic Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree synthesis with skew for memory devices
- Patent number 6,941,533
- Issue date Sep 6, 2005
- LSI Logic Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing-driven placement method utilizing novel interconnect delay m...
- Patent number 6,901,571
- Issue date May 31, 2005
- LSI Logic Corporation
- Dusan Petranovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process of restructuring logics in ICs for setup and hold time opti...
- Patent number 6,810,515
- Issue date Oct 26, 2004
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process for layout of memory matrices in integrated circuits
- Patent number 6,804,811
- Issue date Oct 12, 2004
- LSI Logic Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process layout of buffer modules in integrated circuits
- Patent number 6,760,896
- Issue date Jul 6, 2004
- LSI Logic Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power routing with obstacles
- Patent number 6,757,881
- Issue date Jun 29, 2004
- LSI Logic Corporation
- Alexandre E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for identifying and eliminating bottlenecks in in...
- Patent number 6,757,877
- Issue date Jun 29, 2004
- LSI Logic Corporation
- Robert Stenberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floor plan tester for integrated circuit design
- Patent number 6,701,493
- Issue date Mar 2, 2004
- LSI Logic Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assignment of cell coordinates
- Patent number 6,637,016
- Issue date Oct 21, 2003
- LSI Logic Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell placement in integrated circuit chips to remove cell overlap,...
- Patent number 6,629,304
- Issue date Sep 30, 2003
- LSI Logic Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimal clock timing schedule for an integrated circuit
- Patent number 6,615,397
- Issue date Sep 2, 2003
- LSI Logic Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Netlist resynthesis program based on physical delay calculation
- Patent number 6,557,144
- Issue date Apr 29, 2003
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing recomputation
- Patent number 6,553,551
- Issue date Apr 22, 2003
- LSI Logic Corporation
- Andrej A. Zolotykh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Changing clock delays in an integrated circuit for skew optimization
- Patent number 6,550,045
- Issue date Apr 15, 2003
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Architectural Floorplan for a Structured ASIC Manufactured on a 28...
- Publication number 20140103959
- Publication date Apr 17, 2014
- eASIC Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20120278783
- Publication date Nov 1, 2012
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20110258587
- Publication date Oct 20, 2011
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR FAST UNBALANCED PIPELINE ARCHITECTURE
- Publication number 20090243657
- Publication date Oct 1, 2009
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20090187873
- Publication date Jul 23, 2009
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Built in self test transport controller architecture
- Publication number 20080109688
- Publication date May 8, 2008
- LSI Logic Corporation
- Sergey Gribok
- G11 - INFORMATION STORAGE
Information Patent Application
DENSITY DRIVEN LAYOUT FOR RRAM CONFIGURATION MODULE
- Publication number 20080016482
- Publication date Jan 17, 2008
- LSI Logic Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for avoiding false path pessimism in estimating net delay fo...
- Publication number 20070157143
- Publication date Jul 5, 2007
- Weiqing Guo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing IC clock structures by minimizing clock uncertainty
- Publication number 20060190886
- Publication date Aug 24, 2006
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of buffer insertion to achieve pin specific delays
- Publication number 20060190901
- Publication date Aug 24, 2006
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Density driven layout for RRAM configuration module
- Publication number 20060123373
- Publication date Jun 8, 2006
- LSI Logic Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory tiling architecture
- Publication number 20060104145
- Publication date May 18, 2006
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compact custom layout for RRAM column controller
- Publication number 20060085777
- Publication date Apr 20, 2006
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing IC clock structures by minimizing clock uncertainty
- Publication number 20050010884
- Publication date Jan 13, 2005
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for classifying an integrated circut for optical...
- Publication number 20040123265
- Publication date Jun 24, 2004
- Alexandre Andreev
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Clock tree synthesis with skew for memory devices
- Publication number 20040078766
- Publication date Apr 22, 2004
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Process of restructuring logics in ICs for setup and hold time opti...
- Publication number 20040060012
- Publication date Mar 25, 2004
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Process layout of buffer modules in integrated circuits
- Publication number 20040060027
- Publication date Mar 25, 2004
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESS FOR LAYOUT OF MEMORY MATRICES IN INTEGRATED CIRCUITS
- Publication number 20040060029
- Publication date Mar 25, 2004
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Floor plan tester for integrated circuit design
- Publication number 20030188274
- Publication date Oct 2, 2003
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for identifying and eliminating bottlenecks in in...
- Publication number 20030163797
- Publication date Aug 28, 2003
- LSI Logic Corporation
- Robert Stenberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power routing with obstacles
- Publication number 20030145302
- Publication date Jul 31, 2003
- Alexandre E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLELIZATION OF RESYNTHESIS
- Publication number 20020162085
- Publication date Oct 31, 2002
- Andrej A. Zolotykh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimal clock timing schedule for an integrated circuit
- Publication number 20020091983
- Publication date Jul 11, 2002
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODIFYING TIMING GRAPH TO AVOID GIVEN SET OF PATHS
- Publication number 20010020289
- Publication date Sep 6, 2001
- IVAN PAVISIC
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADVANCED MODULAR CELL PLACEMENT SYSTEM
- Publication number 20010003843
- Publication date Jun 14, 2001
- RANKO SCEPANOVIC
- G06 - COMPUTING CALCULATING COUNTING

Ivan Pavisic

Person

Patents Grantslast 30 patents

Architectural floorplan for a structured ASIC manufactured on a 28...

Method and computer program for generating grounded shielding wires...

Method and apparatus for balancing signal delay skew

Signal delay skew reduction system

Density driven layout for RRAM configuration module

Methods and apparatus for fast unbalanced pipeline architecture

Built in self test transport controller architecture

Optimizing IC clock structures by minimizing clock uncertainty

System for avoiding false path pessimism in estimating net delay fo...

Density driven layout for RRAM configuration module

Method of buffer insertion to achieve pin specific delays

Memory tiling architecture

Compact custom layout for RRAM column controller

Optimizing IC clock structures by minimizing clock uncertainty

Method and system for classifying an integrated circuit for optical...

RRAM backend flow

Clock tree synthesis with skew for memory devices

Timing-driven placement method utilizing novel interconnect delay m...

Process of restructuring logics in ICs for setup and hold time opti...

Process for layout of memory matrices in integrated circuits

Process layout of buffer modules in integrated circuits

Power routing with obstacles

System and method for identifying and eliminating bottlenecks in in...

Floor plan tester for integrated circuit design

Assignment of cell coordinates

Cell placement in integrated circuit chips to remove cell overlap,...

Optimal clock timing schedule for an integrated circuit

Netlist resynthesis program based on physical delay calculation

Timing recomputation

Changing clock delays in an integrated circuit for skew optimization

Patents Applicationslast 30 patents

Architectural Floorplan for a Structured ASIC Manufactured on a 28...

SIGNAL DELAY SKEW REDUCTION SYSTEM

SIGNAL DELAY SKEW REDUCTION SYSTEM

METHODS AND APPARATUS FOR FAST UNBALANCED PIPELINE ARCHITECTURE

SIGNAL DELAY SKEW REDUCTION SYSTEM

Built in self test transport controller architecture

DENSITY DRIVEN LAYOUT FOR RRAM CONFIGURATION MODULE

System for avoiding false path pessimism in estimating net delay fo...

Optimizing IC clock structures by minimizing clock uncertainty

Method of buffer insertion to achieve pin specific delays

Density driven layout for RRAM configuration module

Memory tiling architecture

Compact custom layout for RRAM column controller

Optimizing IC clock structures by minimizing clock uncertainty

Method and system for classifying an integrated circut for optical...

Clock tree synthesis with skew for memory devices

Process of restructuring logics in ICs for setup and hold time opti...

Process layout of buffer modules in integrated circuits

PROCESS FOR LAYOUT OF MEMORY MATRICES IN INTEGRATED CIRCUITS

Floor plan tester for integrated circuit design

System and method for identifying and eliminating bottlenecks in in...

Power routing with obstacles

PARALLELIZATION OF RESYNTHESIS

Optimal clock timing schedule for an integrated circuit

MODIFYING TIMING GRAPH TO AVOID GIVEN SET OF PATHS

ADVANCED MODULAR CELL PLACEMENT SYSTEM