Patent Application
20080109688
This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to the built in self test of memory matrices.
Integrated circuits are often formed using an application specific integrated circuit architecture, which tends to reduce the design costs of the integrated circuit by using predetermined logic blocks in a somewhat customized arrangement to produce an integrated circuit according to a customer's specifications. One aspect of such a customizable integrated circuit design is referred to as reconfigurable random access memory, or RRAM. RRAM contains sets of memories that are placed compactly within a memory matrix.
As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
Testing of embedded memories is one of the most difficult stages of digital system testing. The known design methodologies require the insertion of a separate test controller (such as the memory test controller made by LogicVision, Inc. of San Jose, Calif.) for every embedded memory. This approach is unacceptable for memory matrix testing. Memory matrices contain up to several hundreds memories. It is highly undesirable to increase the matrix size by including hundreds of memory test controllers into the matrix.
There are two main types of digital system testing: production testing and diagnostic testing. Production testing is used to make sure that there are no defects in the integrated circuit. The test result for every memory is just one bit: passed/failed. Every chip must pass all production tests before it is delivered to the customer. Therefore, it is desirable to minimize the overall time that is required by the production testing. When all the memories inside the memory matrix are tested in a standard mode, then the total matrix test time tends to be unacceptably long.
Diagnostic testing can be used to detect the exact position of a defect in a memory. If a production test fails on a memory, then it is desirable to run a diagnostic test on the failed memory to determine exactly which ports or addresses of the memory are defective. Decoding the results of the diagnostic test typically requires analyzing the values output by the memory during the test.
What is needed, therefore, is a built in self test system for matrix memories that overcomes problems such as those described above, at least in part.
The above and other needs are met by a built in self test circuit disposed within a memory matrix. Individual memory cells within the memory matrix are disposed into logical columns. The built in self test circuit has only one memory test controller, which is adapted to initiate test commands and receive test results. Transport controllers are uniquely paired with each one of the logical columns of memory cells. Each of the transport controllers is adapted to receive test commands from the memory test controller, test memory cells within the logical column as instructed by the test commands, receive test results from the logical column of memory cells, and provide the test results to the memory test controller.
The transport controllers are also adapted to selectively operate in three different modes under control of the memory test controller. A first production testing mode simultaneously tests the memory cells in different logical columns, while accumulating the test results for a given logical column with the transport controller associated with the given logical column. A second production testing mode retrieves the accumulated test results from the transport controllers. A diagnostic testing mode tests memory cells within one selected logical column, while simultaneously retrieving the test results for the one selected logical column.
In this manner, the built in self test circuit is able to perform all of the testing typically required by a memory matrix in a very efficient manner. One aspect of this is the simultaneous production testing of many memory cells in the different logical columns. This greatly reduces the time required for production testing the memory matrix. Further, there is only a single test controller for the matrix, instead of a test controller for each logical column of memory cells. By using one test controller with several transport controllers, space on the chip on which the integrated circuit memory matrix is formed is conserved.
Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein:
This various embodiments of the present invention provide an architecture for a transport controller disposed within a memory subsystem. The transport controller is a part of memory matrix built-in self-test system. By “built-in,” it is understood that the test system resides within the integrated circuit, on the monolithic semiconducting chip with the memory system that it tests. It is not externally located, such as on a separate chip or in an external tester. The proposed architecture enables efficient delivery of test signals between a built-in (on chip) memory tester circuit and the memories that reside within the memory matrices. The memory matrix in one embodiment is a structurally organized set of identical memories. In some embodiments, memories in the matrix are arranged into several columns as shown in
Thus, support of both production and diagnostic test modes is a desirable component of reliable memory testing. Therefore, various embodiments of the matrix transport system support detailed testing of any selected memory, in addition to simultaneous testing of large groups of memories.
The embodiments of the present invention describe an architecture of an inner matrix transport controller that is part of a memory matrix transport system. In one embodiment, every matrix column contains one transport controller as shown in
Each transport controller is connected to the memories in the column with which it is associated through an associated test socket, as depicted. The test socket preferably sends test signals to the memories inside the column, enables the selected memory, receives data from the memory outputs, compares this data with the expected data values and sends the comparison result back to the transport controller.
The transport controller for the K-th column is connected to controllers from the previous (K−1)-th column and from the next (K+1)-th column. The controllers are preferably enabled to work in three different modes: (1) simultaneous testing of several memories from different columns, while accumulating the test results inside the controllers, as depicted in
The transport controller ports and interconnections between neighboring controllers are shown in
DATA_IN is a 1-bit input that is connected to the DATA_OUT 1-bit output of the transport controller for the previous column. The DATA_IN input of the transport controller for the first column is controlled from the outside of the matrix RAM system through the DATA matrix input.
ENABLE_IN is a 1-bit input that is connected to the ENABLE_OUT 1-bit output of the transport controller for the previous column. The ENABLE_IN input of the transport controller for the first column is controlled from the outside of the matrix RAM system through the ENABLE matrix input.
CONTROL_IN is a 1-bit input that is connected to the CONTROL_OUT 1-bit output of the transport controller for the previous column. The CONTROL_IN input of the transport controller for the first column is controlled from the outside of matrix RAM system through the CONTROL matrix input.
Therefore, the CONTROL, DATA, and ENABLE signals preferably propagate all the way down through the matrix, from left to right as depicted in the figures. Setting the configuration of all of the transport controllers is preferably accomplished using just these three matrix ports.
DYN_DATA_IN is a multi-bit input that is connected to the DYN_DATA_OUT output of the transport controller for the previous column. The DYN_DATA_IN input of the transport controller for the first column is directly connected to the memory test controller.
DYN_DATA is a multi-bit output that is connected to the test socket for the same column in which the transport controller resides. Test signals from the memory test controller are preferably moving through the DYN_DATA_IN and DYN_DATA_OUT ports of all of the transport controllers, and arriving at the test sockets through the DYN_DATA outputs of the transport controllers.
STAT_CONFIG is a multi-bit output that is also connected to the test socket in the same column. The STAT_CONFIG is preferably used for setting test configuration parameters, such as the memory index or the test type. These parameters are preferably immutable during the test.
TEST_ERROR is a 1-bit input that is also connected to the test socket in the same column. The test socket preferably sets this port to 1 if the memory output data values are not equal to the expected values, which indicates a failure.
RESULT_IN is a 1-bit input that is connected to the RESULT_OUT 1-bit output of the transport controller for the next column. The RESULT_IN input of the transport controller for the last column is connected to VSS. The RESULT_OUT output of the first column goes to the matrix RESULT output.
RESULT_EN_IN is a 1-bit input that is connected to the RESULT_EN_OUT 1-bit output of the transport controller for the next column. The RESULT_EN_IN input of the transport controller for the last column is connected to VSS. The RESULT_EN_OUT output of the first column goes to the matrix RESULT output.
Therefore, the RESULT and RESULT_EN signals preferably propagate all the way down through the matrix, from right to left as depicted in the figures. If RESULT_EN=1, then RESULT preferably represents the memory test result.
Preferably, there is also a clock input, which is not shown in the figures. Preferably, all of the transport controllers in the matrix are working on the same clock.
The inner structure of the preferred embodiment of the transport controller is depicted in
All of the DYN_DATA_IN inputs are preferably connected to data inputs of a set of flip-flops. The corresponding flip-flop outputs are connected to the DYN_DATA and the DYN_DATA_OUT outputs.
The STAT_CONFIG signal preferably consists of several different components such as memory index, test type, and memory output bit index for comparison. Usually in a series of sequential memory tests, only one STAT_CONFIG component is changing. Therefore, to minimize the overall test time, it is desirable to load the different STAT_CONFIG components separately, as described below.
In this example, there are K different parts in the STAT_CONFIG signal. Therefore, the transport controller has (K+1) different states, being: State 0, that scans the test results back from the controller; State 1, that loads the first part of STAT_CONFIG; State 2, that loads the second part of STAT_CONFIG; and State K, that loads the K-th part of STAT_CONFIG.
States 1, 2, . . . , K are preferably used before starting the memory test to set up all the needed configuration parameters. State 0 is preferably used during the test and after the test to retrieve the test results. The current state of the transport controller is preferably set with the CONTROL_IN signal. The CONTROL_IN transport controller input is preferably connected to the input of flip-flop F1. The output of this flip-flop is preferably connected to the CONTROL_OUT port, and with the input A of the state controller.
The state controller is preferably used to set the current state of the transport controller. It preferably has K+1 outputs, labeled SO through Sk. Preferably, only one of these outputs at a time has a value of one, while the others are set at zero. A value of one on the i-th output indicates that the transport controller is in the i-th state.
All the values from state controller outputs preferably go to the first inputs of K+1 AND logic elements AO through Ak. The second inputs of these AND elements are preferably connected to the output of flip-flop F3. This output of flip-flop F3 is preferably also connected to the ENABLE_OUT output of the transport controller. The input of flip-flop F3 is preferably connected to the ENABLE_IN transport controller input. The outputs of the AND elements A1 through Ak are preferably connected to the corresponding K inputs EN1 through ENk of the config controller.
The config controller is preferably used to set the STAT_CONFIG values. If the ENi config controller input value is set to 1, then the i-th part of STAT_CONFIG is shifted from input DIN of the config controller. This input DIN is preferably connected to the output of flip-flop F2. The input of flip-flop F2 is connected to the transport controller input DATA_IN.
The config controller preferably has three different outputs, Z, DOUT, and ACTV. Output Z is preferably connected to the STAT_CONFIG output of the transport controller, output DOUT is preferably connected to the DATA_OUT output of the transport controller, and output ACTV is preferably connected to the third input of the AO AND element. The ACTV signal preferably depends on the transport controller configuration. ACTV is preferably set to one if the appropriate column is active, or in other words, if at least some of the memory in this column is currently under test. If the ACTV is zero, then the corresponding column is passive, or in other words, the memory in the column is not being tested.
The RESULT_OUT transport controller output is preferably connected to the output of flip-flop F4. The input of this flip-flop is preferably connected to the output of mux M1. The control input of this mux is preferably connected to the output of AND element AO. The first input of this mux (the input that corresponds to the zero control value) is preferably connected to the RESULT_IN input of the transport controller, and the second input of the mux M1 is preferably connected to the output of flip-flop F6. The data input of flip-flop F6 is preferably connected to the output of OR element D1. The first input of D1 is preferably connected to the TEST_ERROR input of the transport controller, and the second input of D1 is preferably connected to the output of AND element K1. The first input of K1 is preferably connected to the output of flip-flop F6, and the second input of K1 is preferably connected with the inverted value from the output of A0.
The RESULT_EN_OUT output of the transport controller is preferably connected to the output of the OR element D2. The first input of D2 is preferably connected to the RESULT_EN_IN input of the transport controller. The second input of D2 is preferably connected to the output of A0.
Before starting the memory test, it is preferred to set the STAT_CONFIG test configuration data. To set the i-th component of STAT_CONFIG, it is desirable to perform two steps. First, a special configuration sequence is sent via the CONTROL matrix input to set all of the transport controllers to the i-th state. Then the ENABLE matrix input is set to one and the target STAT_CONFIG values are shifted through the DATA matrix port.
For production testing, it is possible to set the STAT_CONFIG so that several columns are active during the test. These columns are then tested simultaneously. For diagnostic testing, preferably only one column is active during the test.
After loading the configuration, and before the test execution, all of the transport controllers are preferably set to state 0, such as through the CONTROL matrix input. Then the memory test controller starts sending test vectors to the DYN_DATA matrix input. These vectors preferably move through all of the columns to the test sockets. Every active test socket (i.e. the test sockets in the active columns) turns on and starts to send the test vectors to the memory in the respective column that is specified by the STAT_CONFIG values. At the same time, the test socket is analyzing the memory outputs and producing the appropriate TEST_ERROR signal.
During execution of a production test, the ENABLE matrix input is preferably set to zero. Therefore, during the test execution, the TEST_ERROR signal from every active column is accumulated in flip-flop F6. If the test is passed, or in other words if the TEST_ERROR is always zero during the test, then F6 contains zero after the test. If the test is failed, meaning that some errors occurred during the test, then the TEST_ERROR signal will have been set to one sometime during the test, and the flip-flop F6 will contain a value of one after the test.
After a production test, it is desirable to retrieve the accumulated test results from the flip-flops F6 in the active columns. To retrieve the results, the ENABLE matrix input is preferably set to one for just one clock cycle. Therefore, a value of one is applied to the RESULT_EN_OUT output in the active columns, and the value from the flip-flop F6 in each column is applied to the RESULT_OUT output. At the same time, F6 is reset to a value of zero. Thus, a series of ones is observed on the RESULT_EN matrix output, and the corresponding series of test results are observed from the active columns on the RESULT matrix output.
During the execution of a diagnostic test, the ENABLE signal has a value of one all the time. Therefore, the TEST_ERROR signal from the active column goes directly to the RESULT_OUT output of the transport controller for the respective column. At the same time, the RESULT_EN_OUT is set to a value of one. Thus, the RESULT_EN matrix output has a value of one during the test, and the RESULT matrix output signal is the same as the TEST_ERROR signal for the active column.
The foregoing description of preferred embodiments for this invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments are chosen and described in an effort to provide the best illustrations of the principles of the invention and its practical application, and to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.
