Jack Hwang

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-aligned contacts
- Patent number 12,266,571
- Issue date Apr 1, 2025
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 11,887,891
- Issue date Jan 30, 2024
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 11,600,524
- Issue date Mar 7, 2023
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 10,930,557
- Issue date Feb 23, 2021
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 10,629,483
- Issue date Apr 21, 2020
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 10,141,226
- Issue date Nov 27, 2018
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 9,892,967
- Issue date Feb 13, 2018
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 9,508,821
- Issue date Nov 29, 2016
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 9,466,565
- Issue date Oct 11, 2016
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 9,093,513
- Issue date Jul 28, 2015
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 9,054,178
- Issue date Jun 9, 2015
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contacts
- Patent number 8,436,404
- Issue date May 7, 2013
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained NMOS transistor featuring deep carbon doped regions and ra...
- Patent number 8,426,858
- Issue date Apr 23, 2013
- Intel Corporation
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sub-second annealing processes for semiconductor devices
- Patent number 7,892,971
- Issue date Feb 22, 2011
- Intel Corporation
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained NMOS transistor featuring deep carbon doped regions and ra...
- Patent number 7,858,981
- Issue date Dec 28, 2010
- Intel Corporation
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to reduce junction leakage through partial regrowth with ult...
- Patent number 7,790,587
- Issue date Sep 7, 2010
- Intel Corporation
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Temperature measurement with reduced extraneous infrared in a proce...
- Patent number 7,758,238
- Issue date Jul 20, 2010
- Intel Corporation
- Sridhar Govindaraju
- G01 - MEASURING TESTING
Information Patent Grant
Strained NMOS transistor featuring deep carbon doped regions and ra...
- Patent number 7,479,431
- Issue date Jan 20, 2009
- Intel Corporation
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming dual metal complementary metal oxide semiconductor integrat...
- Patent number 7,439,113
- Issue date Oct 21, 2008
- Intel Corporation
- Mark Doczy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash assisted annealing
- Patent number 7,223,660
- Issue date May 29, 2007
- Intel Corporation
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-zone reflecting device for use in flash lamp processes
- Patent number 7,109,443
- Issue date Sep 19, 2006
- Intel Corporation
- Karson L. Knutson
- F27 - FURNACES KILNS OVENS RETORTS
Information Patent Grant
Flash lamp annealing apparatus to generate electromagnetic radiatio...
- Patent number 7,102,141
- Issue date Sep 5, 2006
- Intel Corporation
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Creating shallow junction transistors
- Patent number 6,936,518
- Issue date Aug 30, 2005
- Intel Corporation
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming strained source drain junction field effect transistors
- Patent number 6,911,706
- Issue date Jun 28, 2005
- Intel Corporation
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-thin gate dielectrics
- Patent number 6,808,993
- Issue date Oct 26, 2004
- Intel Corporation
- Christine M. Finnie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming strained source drain junction field effect transistors
- Patent number 6,638,802
- Issue date Oct 28, 2003
- Intel Corporation
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20250239486
- Publication date Jul 24, 2025
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE DO...
- Publication number 20250210587
- Publication date Jun 26, 2025
- Intel Corporation
- Nicolas Butzen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH HIGH CAPA...
- Publication number 20250201768
- Publication date Jun 19, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES FOR HIGH CAPAC...
- Publication number 20250201793
- Publication date Jun 19, 2025
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE CO...
- Publication number 20250201766
- Publication date Jun 19, 2025
- Intel Corporation
- Nicolas Butzen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20240030067
- Publication date Jan 25, 2024
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20230154793
- Publication date May 18, 2023
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20210134673
- Publication date May 6, 2021
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20200251387
- Publication date Aug 6, 2020
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20190051558
- Publication date Feb 14, 2019
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20180096891
- Publication date Apr 5, 2018
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20170040218
- Publication date Feb 9, 2017
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned contacts
- Publication number 20160155815
- Publication date Jun 2, 2016
- Intel Corporation
- Mark T. BOHR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20150270216
- Publication date Sep 24, 2015
- Intel Corporation
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20140151817
- Publication date Jun 5, 2014
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED CONTACTS
- Publication number 20130178033
- Publication date Jul 11, 2013
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned contacts
- Publication number 20110156107
- Publication date Jun 30, 2011
- Mark T. Bohr
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REPLACEMENT METAL GATE FILL
- Publication number 20110147831
- Publication date Jun 23, 2011
- Joseph M. Steigerwald
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Drive current enhancement in tri-gate MOSFETS by introduction of co...
- Publication number 20110147804
- Publication date Jun 23, 2011
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED NMOS TRANSISTOR FEATURING DEEP CARBON DOPED REGIONS AND RA...
- Publication number 20110068403
- Publication date Mar 24, 2011
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Temperature measurement with reduced extraneous infrared in a proce...
- Publication number 20090323759
- Publication date Dec 31, 2009
- Sridhar Govindaraju
- G01 - MEASURING TESTING
Information Patent Application
SUB-SECOND ANNEALING PROCESSES FOR SEMICONDUCTOR DEVICES
- Publication number 20090325392
- Publication date Dec 31, 2009
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Strained NMOS transistor featuring deep carbon doped regions and ra...
- Publication number 20090152601
- Publication date Jun 18, 2009
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Forming dual metal complementary metal oxide semiconductor integrat...
- Publication number 20090020825
- Publication date Jan 22, 2009
- Mark Doczy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS TO REDUCE WAFER EDGE TEMPERATURE AND BREAKAGE OF WAFERS
- Publication number 20080242117
- Publication date Oct 2, 2008
- Panchapakesan Ramanarayanan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to reduce junction leakage through partial regrowth with ult...
- Publication number 20080121882
- Publication date May 29, 2008
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Implant and anneal amorphization process
- Publication number 20070099404
- Publication date May 3, 2007
- Sridhar Govindaraju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Use of active temperature control to provide emmisivity independent...
- Publication number 20060286807
- Publication date Dec 21, 2006
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Strained NMOS transistor featuring deep carbon doped regions and ra...
- Publication number 20060134872
- Publication date Jun 22, 2006
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flash lamp annealing apparatus to generate electromagnetic radiatio...
- Publication number 20060065849
- Publication date Mar 30, 2006
- Intel Corporation
- Jack Hwang
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

Self-aligned contacts

Strained NMOS transistor featuring deep carbon doped regions and ra...

Sub-second annealing processes for semiconductor devices

Strained NMOS transistor featuring deep carbon doped regions and ra...

Method to reduce junction leakage through partial regrowth with ult...

Temperature measurement with reduced extraneous infrared in a proce...

Strained NMOS transistor featuring deep carbon doped regions and ra...

Forming dual metal complementary metal oxide semiconductor integrat...

Flash assisted annealing

Multi-zone reflecting device for use in flash lamp processes

Flash lamp annealing apparatus to generate electromagnetic radiatio...

Creating shallow junction transistors

Forming strained source drain junction field effect transistors

Ultra-thin gate dielectrics

Forming strained source drain junction field effect transistors

Patents Applicationslast 30 patents

SELF-ALIGNED CONTACTS

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE DO...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH HIGH CAPA...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES FOR HIGH CAPAC...

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES AND VOLTAGE CO...

SELF-ALIGNED CONTACTS

SELF-ALIGNED CONTACTS

SELF-ALIGNED CONTACTS

SELF-ALIGNED CONTACTS

SELF-ALIGNED CONTACTS

SELF-ALIGNED CONTACTS

SELF-ALIGNED CONTACTS

Self-aligned contacts

SELF-ALIGNED CONTACTS

SELF-ALIGNED CONTACTS

SELF-ALIGNED CONTACTS

Self-aligned contacts

METHOD FOR REPLACEMENT METAL GATE FILL

Drive current enhancement in tri-gate MOSFETS by introduction of co...

STRAINED NMOS TRANSISTOR FEATURING DEEP CARBON DOPED REGIONS AND RA...

Temperature measurement with reduced extraneous infrared in a proce...

SUB-SECOND ANNEALING PROCESSES FOR SEMICONDUCTOR DEVICES

Strained NMOS transistor featuring deep carbon doped regions and ra...

Forming dual metal complementary metal oxide semiconductor integrat...

APPARATUS TO REDUCE WAFER EDGE TEMPERATURE AND BREAKAGE OF WAFERS

Method to reduce junction leakage through partial regrowth with ult...

Implant and anneal amorphization process

Use of active temperature control to provide emmisivity independent...

Strained NMOS transistor featuring deep carbon doped regions and ra...

Flash lamp annealing apparatus to generate electromagnetic radiatio...