James D. Chlipala

Person

Emmaus, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Adaptive voltage scaling using a serial interface
- Patent number 9,158,359
- Issue date Oct 13, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Michael S. Buonpane
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Critical-path circuit for performance monitoring
- Patent number 8,773,160
- Issue date Jul 8, 2014
- Agere Systems LLC
- James D. Chlipala
- G01 - MEASURING TESTING
Information Patent Grant
Delay circuit having reduced duty cycle distortion
- Patent number 8,680,907
- Issue date Mar 25, 2014
- Agere Systems LLC
- James D. Chlipala
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Critical-path circuit for performance monitoring
- Patent number 8,350,589
- Issue date Jan 8, 2013
- Agere Systems LLC
- James D. Chlipala
- G01 - MEASURING TESTING
Information Patent Grant
Input/output buffer information specification (IBIS) model generati...
- Patent number 8,180,600
- Issue date May 15, 2012
- Agere Systems Inc.
- James D. Chlipala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit performance enhancement using on-chip adaptive v...
- Patent number 8,161,431
- Issue date Apr 17, 2012
- Agere Systems Inc.
- Michael S. Buonpane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for deriving an integrated circuit (IC) clock...
- Patent number 7,786,814
- Issue date Aug 31, 2010
- Agere Systems Inc.
- Michael S. Buonpane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Crosstalk reduction in a backplane employing low-skew clock distrib...
- Patent number 7,366,086
- Issue date Apr 29, 2008
- Agere Systems Inc.
- Christopher J. Abel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for adaptive determination of timing signals o...
- Patent number 7,218,557
- Issue date May 15, 2007
- Agere Systems Inc.
- James D. Chlipala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of making a semiconductor device by balancing shallow trench...
- Patent number 7,174,532
- Issue date Feb 6, 2007
- Agere Systems, INC
- James D. Chlipala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase detector for clock and data recovery
- Patent number 6,700,944
- Issue date Mar 2, 2004
- Agere Systems Inc.
- James D. Chlipala
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuits having improved fusible links
- Patent number 5,025,300
- Issue date Jun 18, 1991
- AT&T Bell Laboratories
- James N. Billig
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laser link blowing in integrateed circuit fabrication
- Patent number 5,021,362
- Issue date Jun 4, 1991
- AT&T Bell Laboratories
- James D. Chlipala
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR SENSING TRANSISTOR MISMATCH
- Publication number 20140132303
- Publication date May 15, 2014
- LSI Corporation
- Scott A. Segan
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHOD FOR SENSING TRANSISTOR AGING EFFECTS
- Publication number 20140136128
- Publication date May 15, 2014
- LSI Corporation
- James D. Chlipala
- G01 - MEASURING TESTING
Information Patent Application
Adaptive Voltage Scaling Using a Serial Interface
- Publication number 20130249290
- Publication date Sep 26, 2013
- LSI Corporation
- Michael S. Buonpane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING
- Publication number 20130088256
- Publication date Apr 11, 2013
- Agere Systems LLC
- James D. Chlipala
- G01 - MEASURING TESTING
Information Patent Application
CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING
- Publication number 20110267096
- Publication date Nov 3, 2011
- Agere Systems Inc.
- James D. Chlipala
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RECONFIGURATION OF EMBEDDED MEMORY HAVING A MULTI-LEVEL CACHE
- Publication number 20100191913
- Publication date Jul 29, 2010
- Agere Systems Inc.
- James D. Chlipala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Performance Enhancement Using On-Chip Adaptive V...
- Publication number 20100115475
- Publication date May 6, 2010
- Michael S. Buonpane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DERIVING AN INTEGRATED CIRCUIT (IC) CLOCK...
- Publication number 20100052800
- Publication date Mar 4, 2010
- Michael S. Buonpane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PCB INCLUDING MULTIPLE CHIPS SHARING AN OFF-CHIP MEMORY, A METHOD O...
- Publication number 20100017569
- Publication date Jan 21, 2010
- Agere Systems Inc.
- Michael S. Buonpane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay Circuit Having Reduced Duty Cycle Distortion
- Publication number 20090108902
- Publication date Apr 30, 2009
- James D. Chlipala
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adaptive Integrated Circuit Clock Skew Correction
- Publication number 20080129357
- Publication date Jun 5, 2008
- James D. Chlipala
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Input/Output Buffer Information Specification (IBIS) Model Generati...
- Publication number 20080059142
- Publication date Mar 6, 2008
- James D. Chlipala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of making a semiconductor device by balancing shallow trench...
- Publication number 20060107243
- Publication date May 18, 2006
- Agere Systems Inc.
- James D. Chlipala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Crosstalk reduction in a backplane employing low-skew clock distrib...
- Publication number 20050088958
- Publication date Apr 28, 2005
- Christopher J. Abel
- G06 - COMPUTING CALCULATING COUNTING

James D. Chlipala

Person

Patents Grantslast 30 patents

Adaptive voltage scaling using a serial interface

Critical-path circuit for performance monitoring

Delay circuit having reduced duty cycle distortion

Critical-path circuit for performance monitoring

Input/output buffer information specification (IBIS) model generati...

Integrated circuit performance enhancement using on-chip adaptive v...

Method and apparatus for deriving an integrated circuit (IC) clock...

Crosstalk reduction in a backplane employing low-skew clock distrib...

Method and apparatus for adaptive determination of timing signals o...

Method of making a semiconductor device by balancing shallow trench...

Phase detector for clock and data recovery

Integrated circuits having improved fusible links

Laser link blowing in integrateed circuit fabrication

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR SENSING TRANSISTOR MISMATCH

APPARATUS AND METHOD FOR SENSING TRANSISTOR AGING EFFECTS

Adaptive Voltage Scaling Using a Serial Interface

CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING

CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING

RECONFIGURATION OF EMBEDDED MEMORY HAVING A MULTI-LEVEL CACHE

Integrated Circuit Performance Enhancement Using On-Chip Adaptive V...

METHOD AND APPARATUS FOR DERIVING AN INTEGRATED CIRCUIT (IC) CLOCK...

PCB INCLUDING MULTIPLE CHIPS SHARING AN OFF-CHIP MEMORY, A METHOD O...

Delay Circuit Having Reduced Duty Cycle Distortion

Adaptive Integrated Circuit Clock Skew Correction

Input/Output Buffer Information Specification (IBIS) Model Generati...

Method of making a semiconductor device by balancing shallow trench...

Crosstalk reduction in a backplane employing low-skew clock distrib...