James E. Shaffer

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Compound differential thread systems
- Patent number 8,602,371
- Issue date Dec 10, 2013
- Twin Turbine Technologies LLC
- James E. Shaffer
- F16 - ENGINEERING ELEMENTS AND UNITS GENERAL MEASURES FOR PRODUCING AND MAINT...
Information Patent Grant
Compound differential thread systems
- Patent number 8,292,243
- Issue date Oct 23, 2012
- Twin Turbine Technologies LLC
- James Shaffer
- F16 - ENGINEERING ELEMENTS AND UNITS GENERAL MEASURES FOR PRODUCING AND MAINT...
Information Patent Grant
Scanning array for obstacle detection and collision avoidance
- Patent number 7,982,662
- Issue date Jul 19, 2011
- Intellex, LLC
- James Shaffer
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor memory remapping
- Patent number 6,163,490
- Issue date Dec 19, 2000
- Micron Technology, Inc.
- James M. Shaffer
Information Patent Grant
Repairable wafer scale integration system
- Patent number 6,131,255
- Issue date Oct 17, 2000
- Micron Technology, Inc.
- Glen G. Atkins
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor memory remapping
- Patent number 6,081,463
- Issue date Jun 27, 2000
- Micron Technology, Inc.
- James M. Shaffer
Information Patent Grant
Method of forming electrically conductive pillars
- Patent number 6,049,977
- Issue date Apr 18, 2000
- Micron Technology, Inc.
- Glen G. Atkins
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale burn-in apparatus and process
- Patent number 5,831,445
- Issue date Nov 3, 1998
- Micron Technology, Inc.
- Glen G. Atkins
- G01 - MEASURING TESTING
Information Patent Grant
Modular memory circuit and method for forming same
- Patent number 5,815,427
- Issue date Sep 29, 1998
- Micron Technology, Inc.
- Eugene H. Cloud
- G11 - INFORMATION STORAGE
Information Patent Grant
Repairable wafer scale integration system
- Patent number 5,798,565
- Issue date Aug 25, 1998
- Micron Technology, Inc.
- Glen G. Atkins
- G01 - MEASURING TESTING
Information Patent Grant
Repairable wafer scale integration system
- Patent number 5,682,064
- Issue date Oct 28, 1997
- Micron Technology, Inc.
- Glen G. Atkins
- G01 - MEASURING TESTING
Information Patent Grant
Wafer scale burn-in apparatus and process
- Patent number 5,570,032
- Issue date Oct 29, 1996
- Micron Technology, Inc.
- Glen G. Atkins
- G01 - MEASURING TESTING
Information Patent Grant
Spare memory arrangement
- Patent number 5,276,834
- Issue date Jan 4, 1994
- Micron Technology, Inc.
- Karl H. Mauritz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing calibrate and track control circuit
- Patent number 5,235,699
- Issue date Aug 10, 1993
- Micron Technology, Inc.
- James M. Shaffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked printed circuit board device
- Patent number 5,200,917
- Issue date Apr 6, 1993
- Micron Technology, Inc.
- James M. Shaffer
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
COMPOUND DIFFERENTIAL THREAD SYSTEMS
- Publication number 20130042707
- Publication date Feb 21, 2013
- TWIN TURBINE TECHNOLOGIES LLC
- James E. Shaffer
- B30 - PRESSES
Information Patent Application
SCANNING ARRAY FOR OBSTACLE DETECTION AND COLLISION AVOIDANCE
- Publication number 20110006943
- Publication date Jan 13, 2011
- INTELLEX, LLC
- JAMES E. SHAFFER
- G01 - MEASURING TESTING
Information Patent Application
COMPOUND DIFFERENTIAL THREAD SYSTEMS
- Publication number 20100108843
- Publication date May 6, 2010
- JAMES SHAFFER
- B30 - PRESSES

James E. Shaffer

Person

Patents Grantslast 30 patents

Compound differential thread systems

Compound differential thread systems

Scanning array for obstacle detection and collision avoidance

Semiconductor memory remapping

Repairable wafer scale integration system

Semiconductor memory remapping

Method of forming electrically conductive pillars

Wafer scale burn-in apparatus and process

Modular memory circuit and method for forming same

Repairable wafer scale integration system

Repairable wafer scale integration system

Wafer scale burn-in apparatus and process

Spare memory arrangement

Timing calibrate and track control circuit

Stacked printed circuit board device

Patents Applicationslast 30 patents

COMPOUND DIFFERENTIAL THREAD SYSTEMS

SCANNING ARRAY FOR OBSTACLE DETECTION AND COLLISION AVOIDANCE

COMPOUND DIFFERENTIAL THREAD SYSTEMS