Jan I. Strandberg

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Printed wiring board with controlled line impedance
- Patent number 6,586,682
- Issue date Jul 1, 2003
- Kulicke & Soffa Holdings, Inc.
- Jan I. Strandberg
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Isolated flip chip of BGA to minimize interconnect stress due to th...
- Patent number 6,509,529
- Issue date Jan 21, 2003
- Kulicke & Soffa Holdings, Inc.
- Sundar Kamath
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Deposited thin film build-up layer dimensions as a method of reliev...
- Patent number 6,440,641
- Issue date Aug 27, 2002
- Kulicke & Soffa Holdings, Inc.
- James L. Lykins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-impedance high-density deposited-on-laminate structures having...
- Patent number 6,323,435
- Issue date Nov 27, 2001
- Kulicke & Soffa Holdings, Inc.
- Jan I. Strandberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolated flip chip or BGA to minimize interconnect stress due to th...
- Patent number 6,299,053
- Issue date Oct 9, 2001
- Kulicke & Soffa Holdings, Inc.
- Sundar Kamath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for controlling stress in thin film layers deposited over a...
- Patent number 6,203,967
- Issue date Mar 20, 2001
- Kulicke & Soffa Holdings, Inc.
- Scott M. Westbrook
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of planarizing thin film layers deposited over a common circ...
- Patent number 6,165,892
- Issue date Dec 26, 2000
- Kulicke & Soffa Holdings, Inc.
- David J. Chazan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Printed wiring board with controlled line impedance
- Publication number 20020139566
- Publication date Oct 3, 2002
- Jan I. Strandberg
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Isolated flip chip or BGA to minimize interconnect stress due to th...
- Publication number 20020011353
- Publication date Jan 31, 2002
- Sundar Kamath
- H01 - BASIC ELECTRIC ELEMENTS

Jan I. Strandberg

Person

Patents Grantslast 30 patents

Printed wiring board with controlled line impedance

Isolated flip chip of BGA to minimize interconnect stress due to th...

Deposited thin film build-up layer dimensions as a method of reliev...

Low-impedance high-density deposited-on-laminate structures having...

Isolated flip chip or BGA to minimize interconnect stress due to th...

Method for controlling stress in thin film layers deposited over a...

Method of planarizing thin film layers deposited over a common circ...

Patents Applicationslast 30 patents

Printed wiring board with controlled line impedance

Isolated flip chip or BGA to minimize interconnect stress due to th...