Janos Kovacs

Person

N. Andover, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sampled delay locked loop insensitive to clock duty cycle
- Patent number 6,147,531
- Issue date Nov 14, 2000
- Analog Devices, Inc.
- Kevin J. McCall
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable pulse slimmer system for low pass ladder filter
- Patent number 6,144,981
- Issue date Nov 7, 2000
- Analog Devices, Inc.
- Janos Kovacs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Burst error limiting symbol detector system
- Patent number 6,067,655
- Issue date May 23, 2000
- STMicroelectronics, N.V.
- Janos Kovacs
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Constrained fixed delay tree search receiver for a MTR=2 encoded co...
- Patent number 5,995,543
- Issue date Nov 30, 1999
- STMicroelectronics N.V.
- Janos Kovacs
- G11 - INFORMATION STORAGE
Information Patent Grant
Composite load circuit
- Patent number 5,793,239
- Issue date Aug 11, 1998
- Analog Devices, Inc.
- Janos Kovacs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Switched capacitance phase locked loop system
- Patent number 5,787,134
- Issue date Jul 28, 1998
- Analog Devices, Inc.
- Janos Kovacs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Read system for implementing PR4 and higher order PRML signals
- Patent number 5,768,320
- Issue date Jun 16, 1998
- Analog Devices, Inc.
- Janos Kovacs
- G11 - INFORMATION STORAGE
Information Patent Grant
Sampled data read channel utilizing charge-coupled devices
- Patent number 5,671,252
- Issue date Sep 23, 1997
- Analog Devices, Inc.
- Janos Kovacs
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic phase selector phase locked loop circuit
- Patent number 5,646,968
- Issue date Jul 8, 1997
- Analog Devices, Inc.
- Janos Kovacs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
All-MOS precision differential delay line with delay a programmable...
- Patent number 5,598,364
- Issue date Jan 28, 1997
- Analog Devices, Inc.
- Kevin J. McCall
- G11 - INFORMATION STORAGE
Information Patent Grant
Intrinsic R2R resistance ladder digital to analog converter
- Patent number 5,525,986
- Issue date Jun 11, 1996
- Analog Devices, Inc.
- Janos Kovacs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid phase locked loop
- Patent number 5,495,512
- Issue date Feb 27, 1996
- Analog Devices, Inc.
- Janos Kovacs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid analog digital automatic gain control gain recovery system
- Patent number 5,422,601
- Issue date Jun 6, 1995
- Analog Devices, Inc.
- Janos Kovacs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Center frequency controlled phase locked loop system
- Patent number 5,414,390
- Issue date May 9, 1995
- Analog Devices, Inc.
- Janos Kovacs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic threshold updating circuit for a maximum likelihood detecto...
- Patent number 5,373,400
- Issue date Dec 13, 1994
- Analog Devices, Inc.
- Janos Kovacs
- G11 - INFORMATION STORAGE

Janos Kovacs

Person

Patents Grantslast 30 patents

Sampled delay locked loop insensitive to clock duty cycle

Programmable pulse slimmer system for low pass ladder filter

Burst error limiting symbol detector system

Constrained fixed delay tree search receiver for a MTR=2 encoded co...

Composite load circuit

Switched capacitance phase locked loop system

Read system for implementing PR4 and higher order PRML signals

Sampled data read channel utilizing charge-coupled devices

Dynamic phase selector phase locked loop circuit

All-MOS precision differential delay line with delay a programmable...

Intrinsic R2R resistance ladder digital to analog converter

Hybrid phase locked loop

Hybrid analog digital automatic gain control gain recovery system

Center frequency controlled phase locked loop system

Dynamic threshold updating circuit for a maximum likelihood detecto...