Javier Soto Gonzalez

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Substrate with embedded stacked through-silicon via die
- Patent number 11,107,766
- Issue date Aug 31, 2021
- Intel Corporation
- Javier Soto Gonzalez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate with embedded stacked through-silicon via die
- Patent number 10,461,032
- Issue date Oct 29, 2019
- Intel Corporation
- Javier Soto Gonzalez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multichip integration with through silicon via (TSV) die embedded i...
- Patent number 9,716,084
- Issue date Jul 25, 2017
- Intel Corporation
- Digvijay A. Raorane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip package having a substrate with a plurality of verticall...
- Patent number 9,559,088
- Issue date Jan 31, 2017
- Intel Corporation
- Javier Soto Gonzalez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multichip integration with through silicon via (TSV) die embedded i...
- Patent number 9,397,079
- Issue date Jul 19, 2016
- Intel Corporation
- Digvijay A. Raorane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming functionalized carrier structures with coreless packages
- Patent number 9,257,380
- Issue date Feb 9, 2016
- Intel Corporation
- Ravi K. Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multichip integration with through silicon via (TSV) die embedded i...
- Patent number 9,000,599
- Issue date Apr 7, 2015
- Intel Corporation
- Digvijay A. Raorane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming functionalized carrier structures with coreless packages
- Patent number 8,987,065
- Issue date Mar 24, 2015
- Intel Corporation
- Ravi K. Nailla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor package with embedded die and its methods of fabrication
- Patent number 8,901,724
- Issue date Dec 2, 2014
- Intel Corporation
- John Stephen Guzek
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Die-stacking using through-silicon vias on bumpless build-up layer...
- Patent number 8,786,066
- Issue date Jul 22, 2014
- Intel Corporation
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip package having a substrate with a plurality of verticall...
- Patent number 8,736,065
- Issue date May 27, 2014
- Intel Corporation
- Javier Soto Gonzalez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming functionalized carrier structures with coreless packages
- Patent number 8,618,652
- Issue date Dec 31, 2013
- Intel Corporation
- Ravi K Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Forming die backside coating structures with coreless packages
- Patent number 8,466,559
- Issue date Jun 18, 2013
- Intel Corporation
- Rahul N. Manepalli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate with embedded stacked through-silicon via die
- Patent number 8,421,245
- Issue date Apr 16, 2013
- Intel Corporation
- Javier Soto Gonzalez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with package to package connection
- Patent number 7,952,182
- Issue date May 31, 2011
- Intel Corporation
- Nicholas Randolph Watts
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE
- Publication number 20200020636
- Publication date Jan 16, 2020
- Intel Corporation
- Javier Soto GONZALEZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTICHIP INTEGRATION WITH THROUGH SILICON VIA (TSV) DIE EMBEDDED I...
- Publication number 20160322344
- Publication date Nov 3, 2016
- Intel Corporation
- Digvijay A. Raorane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES
- Publication number 20150179559
- Publication date Jun 25, 2015
- Intel Corporation
- Ravi K. Nalla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTICHIP INTEGRATION WITH THROUGH SILICON VIA (TSV) DIE EMBEDDED I...
- Publication number 20150171067
- Publication date Jun 18, 2015
- Intel Corporation
- Digvijay A. Raorane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTICHIP INTEGRATION WITH THROUGH SILICON VIA (TSV) DIE EMBEDDED I...
- Publication number 20140332975
- Publication date Nov 13, 2014
- Digvijay A. Raorane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGE HAVING A SUBSTRATE WITH A PLURALITY OF VERTICALL...
- Publication number 20140248742
- Publication date Sep 4, 2014
- Javier Soto Gonzalez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES
- Publication number 20140084467
- Publication date Mar 27, 2014
- Ravi K. Nalla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE
- Publication number 20130147043
- Publication date Jun 13, 2013
- Javier Soto Gonzalez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGE HAVING A SUBSTRATE WITH A PLURALITY OF VERTICALL...
- Publication number 20120161331
- Publication date Jun 28, 2012
- Javier Soto Gonzalez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE
- Publication number 20120161316
- Publication date Jun 28, 2012
- Javier Soto Gonzalez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING DIE BACKSIDE COATING STRUCTURES WITH CORELESS PACKAGES
- Publication number 20120153494
- Publication date Jun 21, 2012
- Rahul N. Manepalli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER...
- Publication number 20120074581
- Publication date Mar 29, 2012
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES
- Publication number 20110254124
- Publication date Oct 20, 2011
- Ravi K. Nalla
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Semiconductor package with embedded die and its methods of fabrication
- Publication number 20110215464
- Publication date Sep 8, 2011
- Intel Corporation
- John Stephen Guzek
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Coreless substrate package with symmetric external dielectric layers
- Publication number 20090321932
- Publication date Dec 31, 2009
- Javier Soto Gonzalez
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Javier Soto Gonzalez

Person

Patents Grantslast 30 patents

Substrate with embedded stacked through-silicon via die

Substrate with embedded stacked through-silicon via die

Multichip integration with through silicon via (TSV) die embedded i...

Multi-chip package having a substrate with a plurality of verticall...

Multichip integration with through silicon via (TSV) die embedded i...

Forming functionalized carrier structures with coreless packages

Multichip integration with through silicon via (TSV) die embedded i...

Forming functionalized carrier structures with coreless packages

Semiconductor package with embedded die and its methods of fabrication

Die-stacking using through-silicon vias on bumpless build-up layer...

Multi-chip package having a substrate with a plurality of verticall...

Forming functionalized carrier structures with coreless packages

Forming die backside coating structures with coreless packages

Substrate with embedded stacked through-silicon via die

Semiconductor device with package to package connection

Patents Applicationslast 30 patents

SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE

MULTICHIP INTEGRATION WITH THROUGH SILICON VIA (TSV) DIE EMBEDDED I...

FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES

MULTICHIP INTEGRATION WITH THROUGH SILICON VIA (TSV) DIE EMBEDDED I...

MULTICHIP INTEGRATION WITH THROUGH SILICON VIA (TSV) DIE EMBEDDED I...

MULTI-CHIP PACKAGE HAVING A SUBSTRATE WITH A PLURALITY OF VERTICALL...

FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES

SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE

MULTI-CHIP PACKAGE HAVING A SUBSTRATE WITH A PLURALITY OF VERTICALL...

SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE

FORMING DIE BACKSIDE COATING STRUCTURES WITH CORELESS PACKAGES

DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER...

FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES

Semiconductor package with embedded die and its methods of fabrication

Coreless substrate package with symmetric external dielectric layers