Patent Application
20110254124
As semiconductor technology advances for higher processor performance, advances in packaging architectures may include coreless bumpless build-up Layer (BBUL-C) package architectures and other such assemblies. Current process flows for BBUL-C packages involve building of the substrate on a temporary core/carrier capped with copper foil, which is etched off after the package is separated from the core.
While the specification concludes with claims particularly pointing out and distinctly claiming certain embodiments of the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
a-1h represent methods of forming structures according to an embodiment of the present invention.
a-2e represent methods of forming structures according to an embodiment of the present invention.
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the embodiments. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the embodiments. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the embodiments is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
Methods and associated structures of forming and utilizing a microelectronic structure, such as a package structure, are described. Those methods may comprise Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material. Methods of the embodiments enable the functionalizing of the carrier material to create functionalized carrier structures, such as an EMI shield, a stiffener, a heat spreader, an inductor and PoP land structures, for example.
a-1h illustrate embodiments of a method of forming a microelectronic structure, such as a package structure, for example.
In an embodiment, the carrier material 100 may comprise two layers of a conductive material, such as but not limited to copper, for example, that may be separated by a thin etching barrier (stop) layer 102. In an embodiment, the etch stop layer 102 may comprise such materials as nickel, for example, but may comprise any such material that may serve to comprise an etch stop layer to facilitate the stopping of an etch between carrier layers. In an embodiment, the etch stop layer 102 may serve to aid in the formation of a cavity 104 (
The cavity 104 may be formed in one layer of the carrier material, such as by removing a portion of the bottom carrier material layer 100′. The cavity 104 may be formed utilizing any suitable removal process, such as an etching process, such as are known in the art. For example, a masking material may be laminated onto the bottom layer of the carrier material 100′ and the carrier material 100′ may be pattered to form the cavity 104, wherein a die may be subsequently placed therein. The etch stop layer 102 between the carrier material layers 100, 100′ may serve as an etch stop for the cavity 104 formation and may define a flat surface to place the die on to. The cavity 104 as formed may comprise a bottom portion 101 an angled portion 105, and a top portion 107, wherein the top portion comprises a portion of the etch stop layer 102.
In other embodiments, the cavity 104 may be formed, and the bottom portion of the carrier material 100 may remain substantially flat, as in
In an embodiment, the adhesive film can be used as a permanent part of a final package to protect the backside 111 of the die 106, to provide a surface for marking, and/or to manage any warpage that may occur within the die 106, for example. In an embodiment, the adhesive may comprise a back-side film (DBF) that may be applied to the back side 111 of the die 106 prior to placement. The DBF may be filled with metallic particles (e.g, copper or silver), for example, to enhance conductivity when subsequently connected to a heat spreader device, such as a micro-channel heat spreader, for example.
A dielectric material 110 may be formed on the carrier material 100′ and adjacent the die 106 that is in the cavity 104 of the carrier material 100′ (
In an embodiment, vias 113 may be formed in the dielectric material 110 in a die area landing of the die 106, wherein die pads, for example copper die pads, may be exposed on the active side 112 of the die 106 (
In an embodiment, when the build-up is complete, the top carrier material 100 and the etch stop layer 102 may be removed, exposing the bottom carrier material 100′ that is attached to the coreless package structure 120 (
In an embodiment, by adjusting the right material properties, the presence of the carrier material 100′ (which may comprise a copper ring in some cases) around the die 106 can alleviate the warpage of the coreless package structure 120. In some prior art coreless BBUL package structures, very small form factor (˜12×12 mm) products may be employed. Larger form factor products will benefit by the addition of the stiffener 100′ to the BBUL package structure 120 without adding additional post-packaging cost, since attachment of a stiffener post-package manufacturing will add cost to the package. Thus, the stiffener of the embodiments herein enable the extension of this technology to more cost sensitive markets/architectures, like chipset, and low-z height mobile CPU's, for example. In other embodiments, the carrier material 100′ may be functionalized/formed to serve several additional functions, such as but not limited to the formation of a heat spreader, EMI (electro magnetic interference) shielding, etc. In an embodiment, a top surface 115 of the at least one functionalized carrier structure 100′ is coplanar with a top surface 113 of the coreless bumpless buildup package 120 and is coplanar with the backside 111 of the die 106.
In another embodiment, a semi-additive process may be used to form die pad interconnect structures 212 on die pads of a die 206 and a first metal layer 214 may be formed on a dielectric material 210 adjacent the die 206 (
Subsequent layers may then be formed using standard substrate SAP build-up methods to form the remainder of the package 220, wherein further dielectric layers 210′ and metallization layers 214′ may be formed upon each other to form a coreless substrate portion 216 of a coreless package structure 220 by utilizing the buildup process (
d depicts a top view of a spiral inductor structure 201 shown on either side of the die 206 with vias underneath start and finish point to connect them electrically into the package 220 (vias not shown). In another embodiment, after the top layer of the carrier material 200 and the etch stop layer 202 are removed, the carrier material bottom layer 200′ may be patterned to form PoP (Package on Package) land structures 203 adjacent the die 206 (
Additional processing may be done to form the desired surface finish on top of the PoP structures 203, in some cases. An advantage of the present embodiment is that a top surface 231 of the POP pads 203 are flush/coplanar with a top surface (backside) 230 of the die 206, which provides for improved Z-height and ability to attach another package to the coreless package structure 220.
One or more of the components shown in system 300 may be included in/and or may include one or more integrated circuit packages, such as the package structures including the functionalized carrier material of
These elements perform their conventional functions well known in the art. In particular, memory device 320 may be used in some cases to provide long-term storage for the executable instructions for a method for forming packaged structures in accordance with embodiments of the present invention, and in other embodiments may be used to store on a shorter term basis the executable instructions of a method for forming package structures in accordance with embodiments of the present invention during execution by processor 310. In addition, the instructions may be stored, or otherwise associated with, machine accessible mediums communicatively coupled with the system, such as compact disk read only memories (CD-ROMs), digital versatile disks (DVDs), and floppy disks, carrier waves, and/or other propagated signals, for example. In one embodiment, memory device 320 may supply the processor 310 with the executable instructions for execution.
System 300 may include computers (e.g., desktops, laptops, hand-helds, servers, Web appliances, routers, etc.), wireless communication devices (e.g., cellular phones, cordless phones, pagers, personal digital assistants, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, camcorders, digital cameras, MP3 (Motion Picture Experts Group, Audio Layer 3) players, video games, watches, etc.), and the like.
Benefits of the embodiments enable a new packaging architecture that can meet design requirements for future mobile/handheld system on a chip (SoC) processors at roughly half the cost of current package architectures. Various embodiments enable the addition of warpage improvement stiffeners, EMI shielding, inductor structures, PoP land structures and heat spreader structures without added post-package manufacturing cost. The POP land structures of the various embodiments have the added benefit of being formed without the need for an interposer to account for the die thickness in the package.
Prior art process flows for coreless BBUL packages typically involve building of the substrate on a temporary core/carrier capped with copper foil, which is etched off after the package is separated from the core. The embodiments herein include methods to functionalize the carrier material/copper foil on the carrier for uses such as heat spreaders, warpage improvement, electromagnetic interference (EMI) shielding for RF components, creating pads for Package on Package (POP) applications etc. thus reducing cost and increasing throughput.
Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims. In addition, it is appreciated that various microelectronic structures, such as package structures, are well known in the art. Therefore, the Figures provided herein illustrate only portions of an exemplary microelectronic device that pertains to the practice of the present invention. Thus the present invention is not limited to the structures described herein.
