1. Field
The present description relates to the field of substrates for use in packaging and mounting semiconductor and micromechanical dies, and in particular to building coreless substrates over a temporary core and then removing the core prior to finishing the substrate.
2. Related Art
Integrated circuits and micromechanical structures are typically formed in groups on a wafer. The wafer is a substrate, typically of silicon or the like and then is cut up into dies, so that each die contains one integrated circuit or micromechanical structure. Each die is then mounted to a substrate and is then typically packaged. The substrate connects the die to a printed circuit board, socket or other connection. The package supports or protect the die and may also provide other functions such as isolation, insulation, thermal control and more.
Substrates for this purpose are typically made of woven glass layers pre-impregnated with an epoxy resin material, such as the prepreg laminate FR-4 commonly used for printed circuit boards. Connection pads and conductive copper traces are then formed on the substrate to provide the interconnection between the die and the system to which it is mounted.
In order to reduce z-height and improve electrical connection, coreless substrates are used. In the coreless substrate, the connection pads and conductive traces are first formed over a core. After these structures have been created, the core upon which the connections are formed is removed. Since a prepreg core may be 800 or more microns thick, removing it can reduce the height of the substrate by more than half. For some coreless technologies a copper core is used rather than a prepreg core.
Creating a coreless substrate, however, presents challenges in providing sufficient structural rigidity and appropriate thermal properties. In addition, there are limitations in forming the layers on the core because only one side of the eventual substrate is accessible. The other side is blocked by the temporary core.
According to an embodiment of the invention, a protective step is used to separate a coreless substrate from the temporary core before the substrate is submitted to a SR (Solder Resist) process. Once separated, thin package SR may be used to transform the BE (Back End) of a coreless substrate to a standard building FCBGA (Flip Chip Ball Grid Array) process. This allows many conventional chemistry and processing steps to be used. It also allows coreless substrates routing to be formed on both sides of the substrate.
It may be difficult to produce coreless packages using existing materials. Some processes have been proposed which require new surface chemistry. A new surface chemistry imposes new capital investments for substrate suppliers, for developing experience and consistency, and for creating the surface finishes between top and bottom layers.
According to an embodiment of the invention, the assembly process may use a very similar external SR layer to substrates with cores. This simplifies the manufacture and also the integration of coreless packages and those with cores into larger systems. Such a single surface finish chemistry allows for better shock performance and minimizes assembly transparency issues. According to an embodiment of the invention, Ni (Nickel) may be used as a barrier for a Cu (Copper) chemical etch.
According to an embodiment of the invention the inner side of a package formed with a coreless substrate will have a thicker Ni layer. In one example, the Ni layer is approximately one hundred times and at least ten times thicker than the adjacent layers, for example Pd and Au. The thicker Ni layer may also have a different grain structure. In addition, as described below, SR may be formed on both sides of the substrate rather than on only one side. In other words, a dual side SR may be produced for coreless ultra thin packages.
Referring to
The illustrated package is an ultra thin package with a coreless substrate. In this example, the package 68 has a die 66, containing the electronic or micromechanical system, attached to a coreless substrate 24. The coreless substrate has solder balls 74 opposite the die for attachment to the motherboard 76.
As shown, the die 66 attaches to the substrate 24 with a ball grid array 80 through a series of contact pads 78. The contacts 78 lead to vias 70 that conduct through to the solder balls 74. The coreless substrate 24 may include a network of Cu traces (not shown) that run horizontally to connect vias 70 to each other. The particular number of pads and solder balls and the connections between them may be adapted to suit any particular implementation.
The package may also include additional components (not shown) such as a cover, a heat spreader, a cooling device, such as fins, liquid cooling contacts and other components. The package may also include additional dies, external connection ports, and additional contacts on the top or sides of the package. A wide variety of additional structures may be added or adapted to the package, depending on the particular implementation.
As mentioned above, the package may also be adapted for use with a socket (not shown) or other receptacle. The package may accordingly include clamping surfaces, retention features and conductive connectors to features on the socket.
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The figures above describe an example of manufacturing a coreless substrate 68. The number of layers may be modified to suit any particular implementation. After the top layer Cu plating, DFR lamination 26 may be used as a protective layer. This allows the temporary core 2 to be separated using electrolytic Ni as a Cu etching barrier.
The DFR 26 may then be stripped as shown in
The exposed metal surfaces 27, 34 may then be finished with, for example, an electroless Ni/Pd/Au coating 36, 38. as shown in
In
Finally, at
As an alternative SR printing may be performed on both sides either with or without the surface finish 36, 38.
As another alternative after the core separation (
As another alternative, instead of a DFR lamination PET (Poly Ethylene Terephthalate) lamination may be used. The PET lamination may be applied after the top layer Cu plating. The PET lamination serves as a protective layer during core separation. Electrolytic Ni may still function as a Cu etching barrier. The PET lamination may then be removed. SR coating may be applied to one or both sides and the surface finish electroless Ni/Pd/Au layer may be applied as shown in the figures. While in the present example, the SR metal layer may be formed from a variety of different materials. This Ni/Pd/Au layer may be a thick layer of Ni is followed by Pd plating and then Au plating.”
As shown in the Figures, SR may be used to cover the substrate's insulator lamination even with different types of contacts. On the top side of the substrate of
The SR protection on the bottom side also allows for connections on the bottom surface to be routed within the substrate. As shown in
Since this layer is typically exposed to the environment in the finished substrate, routing cannot readily be used on the inner layer. Any routing may be unreliable. By applying the SR layer 32 over the bottom side as shown in
The top and bottom substrate structures are identical in
At block 208, the first layer of insulator is laminated over the contact pads. This begins the formation of the portion that will eventually form the structure of the substrate. At block 210, the conductive vias through the insulator down to the contact pads are formed. This is done by first laser drilling and then coating with copper, or any other appropriate conductor. At block 212, contact pads are formed over the vias by patterning, filling with copper and then etching.
At block 214, the process returns to block 208 until sufficient layers have been formed. In brief, the lamination and formation of vias is repeated to form the desired number of additional layers of substrate. This thickens and strengthens the substrate to later support the die.
At block 216, a DFR lamination is applied to the structure to protect the vias and contact pads. Then at block 218, the temporary core is separated from the substrate and the DFR is stripped off.
At block 220, SR is applied and patterned to create openings for the contact pads. At block 222, the contact pads are formed by an SF process using Ni, then Pd, then Au. Finally, the contact pads are finished at block 224 with the appropriate surfaces, such as solder balls for a C4 pad. Optionally, additional finishing steps may be used for the opposite side, the side that was formally attached to the temporary core.
The finished substrate may then be attached to one or more dies. Leads and other components may be attached, if desired. The resulting structure may then be used to form a package as suggested in
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Various additional layers and/or structures may be included and/or described features may be omitted in other embodiments.
Various operations are described as multiple discrete operations to aid in understanding the description. However, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and described operations may be omitted.
Many modifications and variations are possible in light of the above teachings. Various equivalent combinations and substitutions may be made for various components and operations shown in the figures. The scope of the invention is not to be limited by this detailed description, but rather by the claims appended hereto.
The example cleaning processes described above are provided only as examples. There may be other and different chemical processes that break down, convert to gas or otherwise eliminate photo-induced defects on a mask. The example above show how combinations of illumination, heat, and exposure to gases such as air, oxygen, and water vapor may partially or completely eliminate these compounds and reduce the amount of or completely eliminate a wide range of different types of photo-induced defects from a photomask surface. The particular combination of illumination, heat, vacuum and other parameters may be selected with the above examples in mind. Alternatively, the particular combination may be selected based on the parameters described above and then optimized using trial and error.
A lesser or more complex cleaning chamber, set of cleaning operations, photomask, and pellicle may be used than those shown and described herein. Therefore, the configurations may vary from implementation to implementation depending upon numerous factors, such as price constraints, performance requirements, technological improvements, or other circumstances. Embodiments of the invention may also be applied to other types of photolithography systems that use different materials and devices (e.g. EUV lithography) than those shown and described herein. While the description above refers primarily to 193 nm photolithography equipment and techniques, the invention is not so limited and may be applied to a wide range of other wavelengths and other process parameters. In addition, the invention may be applied to the production of semiconductors, microelectronics, micromachines and other devices that use photolithography technology.
In the description above, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. For example, well-known equivalent materials may be substituted in place of those described herein, and similarly, well-known equivalent techniques may be substituted in place of the particular processing techniques disclosed. In addition, steps and operations may be removed or added to the operations described to improve results or add additional functions. In other instances, well-known circuits, structures and techniques have not been shown in detail to avoid obscuring the understanding of this description.
While the embodiments of the invention have been described in terms of several examples, those skilled in the art may recognize that the invention is not limited to the embodiments described, but may be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.