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Jay Nejedlo
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Wilsonville, OR, US
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Patents Grants
last 30 patents
Information
Patent Grant
Test, validation, and debug architecture
Patent number
10,198,333
Issue date
Feb 5, 2019
Intel Corporation
Mark B. Trobough
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Robust memory link testing using memory controller
Patent number
8,868,992
Issue date
Oct 21, 2014
Intel Corporation
Bryan L. Spry
G11 - INFORMATION STORAGE
Information
Patent Grant
Graphical user interface for creation of IBIST tests
Patent number
7,590,504
Issue date
Sep 15, 2009
Asset Intertech, Inc.
James Ernest Chorn
G01 - MEASURING TESTING
Information
Patent Grant
User data driven test control software application the requires no...
Patent number
7,562,274
Issue date
Jul 14, 2009
Asset Intertech, Inc.
James Ernest Chorn
G01 - MEASURING TESTING
Information
Patent Grant
Built-in self test for memory interconnect testing
Patent number
7,536,267
Issue date
May 19, 2009
Intel Corporation
David Zimmerman
G11 - INFORMATION STORAGE
Information
Patent Grant
High performance serial bus testing methodology
Patent number
7,464,307
Issue date
Dec 9, 2008
Intel Corporation
Jay J. Nejedlo
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Automated BIST execution scheme for a link
Patent number
7,437,643
Issue date
Oct 14, 2008
Intel Corporation
Rahul Khanna
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Reusable, built-in self-test methodology for computer systems
Patent number
7,155,370
Issue date
Dec 26, 2006
Intel Corporation
Jay Nejedlo
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Testing methodology and apparatus for interconnects
Patent number
7,047,458
Issue date
May 16, 2006
Intel Corporation
Jay Nejedlo
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Push button mode automatic pattern switching for interconnect built...
Patent number
6,826,100
Issue date
Nov 30, 2004
Intel Corporation
David G. Ellis
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
TRANSPARENTLY MONITORING POWER DELIVERY IN A PROCESSOR
Publication number
20170052586
Publication date
Feb 23, 2017
Intel Corporation
Jay Nejedlo
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
TEST, VALIDATION, AND DEBUG ARCHITECTURE
Publication number
20150127983
Publication date
May 7, 2015
Intel Corporation
Mark B. Trobough
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
ROBUST MEMORY LINK TESTING USING MEMORY CONTROLLER
Publication number
20110161752
Publication date
Jun 30, 2011
BRYAN L. SPRY
G11 - INFORMATION STORAGE
Information
Patent Application
USER DATA DRIVEN TEST CONTROL SOFTWARE APPLICATION THAT REQUIRES NO...
Publication number
20070079199
Publication date
Apr 5, 2007
ASSET InterTech, Inc.
James Ernest Chorn
G01 - MEASURING TESTING
Information
Patent Application
GRAPHICAL USER INTERFACE FOR CREATION OF IBIST TESTS
Publication number
20070073507
Publication date
Mar 29, 2007
ASSET InterTech, Inc.
James Ernest Chorn
G01 - MEASURING TESTING
Information
Patent Application
Automated BIST execution scheme for a link
Publication number
20070011536
Publication date
Jan 11, 2007
Rahul Khanna
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Built-in self test for memory interconnect testing
Publication number
20060080058
Publication date
Apr 13, 2006
David Zimmerman
G11 - INFORMATION STORAGE
Information
Patent Application
Built-in self test for memory interconnect testing
Publication number
20050080581
Publication date
Apr 14, 2005
David Zimmerman
G11 - INFORMATION STORAGE
Information
Patent Application
High performance serial bus testing methodology
Publication number
20040204912
Publication date
Oct 14, 2004
Jay J. Nejedlo
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
On-die pattern generator for high speed serial interconnect built-i...
Publication number
20040193986
Publication date
Sep 30, 2004
Karthisha S. Canagasaby
G01 - MEASURING TESTING
Information
Patent Application
Method and apparatus for interconnect built-in self test based syst...
Publication number
20040193976
Publication date
Sep 30, 2004
Thomas M. Slaight
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Reusable, built-in self-test methodology for computer systems
Publication number
20040186688
Publication date
Sep 23, 2004
Jay Nejedlo
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Pre-announce signaling for interconnect built-in self test
Publication number
20040117708
Publication date
Jun 17, 2004
David G. Ellis
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Push button mode automatic pattern switching for interconnect built...
Publication number
20040117707
Publication date
Jun 17, 2004
David G. Ellis
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Testing methodology and apparatus for interconnects
Publication number
20040117709
Publication date
Jun 17, 2004
Jay Nejedlo
G06 - COMPUTING CALCULATING COUNTING