Jesse S. WANG

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Keeper-free volatile memory system
- Patent number 12,131,775
- Issue date Oct 29, 2024
- NVIDIA Corp.
- Lalit Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Slew signal shaper circuit using two signal paths
- Patent number 11,854,660
- Issue date Dec 26, 2023
- NVIDIA Corp.
- Lalit Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Area efficient memory cell read disturb mitigation
- Patent number 11,804,262
- Issue date Oct 31, 2023
- NVIDIA Corp.
- Lalit Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Three state latch
- Patent number 10,141,930
- Issue date Nov 27, 2018
- NVIDIA Corporation
- Andreas J. Gotterba
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Three state latch
- Patent number 10,009,027
- Issue date Jun 26, 2018
- NVIDIA Corporation
- Andreas J. Gotterba
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Handshaking sense amplifier
- Patent number 9,418,730
- Issue date Aug 16, 2016
- NVIDIA Corporation
- Andreas J. Gotterba
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SHARED METAL WIRE CAPACITANCE FOR NEGATIVE BIT-LINE
- Publication number 20240420748
- Publication date Dec 19, 2024
- NVIDIA Corp.
- Cagri Erbagci
- G11 - INFORMATION STORAGE
Information Patent Application
LEVEL-SHIFTER HAVING A WIDE OPERATING RANGE, A FAST OUTPUT FALL DEL...
- Publication number 20240405776
- Publication date Dec 5, 2024
- NVIDIA Corporation
- Stefan P. Sywyk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTENTION-FREE DUAL-VOLTAGE LOGIC CELL
- Publication number 20240395293
- Publication date Nov 28, 2024
- NVIDIA Corp.
- Lalit Gupta
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-VOLTAGE RAM USED TO CROSS CLOCK AND VOLTAGE DOMAINS
- Publication number 20240296875
- Publication date Sep 5, 2024
- NVIDIA Corporation
- Jason Golbus
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL PORT DUAL POWER RAIL MEMORY ARCHITECTURE
- Publication number 20240161815
- Publication date May 16, 2024
- NVIDIA Corp.
- Lalit Gupta
- G11 - INFORMATION STORAGE
Information Patent Application
KEEPER-FREE VOLATILE MEMORY SYSTEM
- Publication number 20230267992
- Publication date Aug 24, 2023
- NVIDIA Corp.
- Lalit Gupta
- G11 - INFORMATION STORAGE
Information Patent Application
SLEW SIGNAL SHAPER CIRCUIT
- Publication number 20230197127
- Publication date Jun 22, 2023
- NVIDIA Corp.
- Lalit Gupta
- G11 - INFORMATION STORAGE
Information Patent Application
AREA EFFICIENT MEMORY CELL READ DISTURB MITIGATION
- Publication number 20220406371
- Publication date Dec 22, 2022
- NVIDIA Corp.
- Lalit Gupta
- G11 - INFORMATION STORAGE
Information Patent Application
THREE STATE LATCH
- Publication number 20170207783
- Publication date Jul 20, 2017
- NVIDIA Corporation
- Andreas J. GOTTERBA
- G11 - INFORMATION STORAGE
Information Patent Application
PIPELINED ONE CYCLE THROUGHPUT FOR SINGLE-PORT 6T RAM
- Publication number 20140355362
- Publication date Dec 4, 2014
- Jesse S. WANG
- G11 - INFORMATION STORAGE
Information Patent Application
THREE STATE LATCH
- Publication number 20140354330
- Publication date Dec 4, 2014
- Andreas J. GOTTERBA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HANDSHAKING SENSE AMPLIFIER
- Publication number 20140355334
- Publication date Dec 4, 2014
- Andreas J. GOTTERBA
- G11 - INFORMATION STORAGE

Jesse S. WANG

Person

Patents Grantslast 30 patents

Keeper-free volatile memory system

Slew signal shaper circuit using two signal paths

Area efficient memory cell read disturb mitigation

Three state latch

Three state latch

Handshaking sense amplifier

Patents Applicationslast 30 patents

SHARED METAL WIRE CAPACITANCE FOR NEGATIVE BIT-LINE

LEVEL-SHIFTER HAVING A WIDE OPERATING RANGE, A FAST OUTPUT FALL DEL...

CONTENTION-FREE DUAL-VOLTAGE LOGIC CELL

MULTI-VOLTAGE RAM USED TO CROSS CLOCK AND VOLTAGE DOMAINS

DUAL PORT DUAL POWER RAIL MEMORY ARCHITECTURE

KEEPER-FREE VOLATILE MEMORY SYSTEM

SLEW SIGNAL SHAPER CIRCUIT

AREA EFFICIENT MEMORY CELL READ DISTURB MITIGATION

THREE STATE LATCH

PIPELINED ONE CYCLE THROUGHPUT FOR SINGLE-PORT 6T RAM

THREE STATE LATCH

HANDSHAKING SENSE AMPLIFIER