Jody A. Fronheiser

Person

Delmar, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device and method for reduced bias threshold instability
- Patent number 11,417,759
- Issue date Aug 16, 2022
- General Electric Company
- Stephen Daley Arthur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field-effect transistors with a grown silicon-germanium channel
- Patent number 10,680,065
- Issue date Jun 9, 2020
- GlobalFoundries Inc.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface area and Schottky barrier height engineering for contact tr...
- Patent number 10,643,894
- Issue date May 5, 2020
- International Business Machines Corporation
- Jody Fronheiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface area and Schottky barrier height engineering for contact tr...
- Patent number 10,643,893
- Issue date May 5, 2020
- International Business Machines Corporation
- Jody Fronheiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method for reduced bias threshold instability
- Patent number 10,367,089
- Issue date Jul 30, 2019
- General Electric Company
- Stephen Daley Arthur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a vertical transistor device
- Patent number 10,170,616
- Issue date Jan 1, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical transport field effect transistors
- Patent number 10,170,617
- Issue date Jan 1, 2019
- Globalfoundries
- Jiseok Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically insulated fin structure(s) with alternative channel ma...
- Patent number 10,163,677
- Issue date Dec 25, 2018
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated structure having an epitaxial SiGe layer e...
- Patent number 10,032,912
- Issue date Jul 24, 2018
- STMicroelectronics, Inc.
- Pierre Morin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming fin isolation regions under tensile-strained fin...
- Patent number 10,026,659
- Issue date Jul 17, 2018
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Common fabrication of multiple FinFETs with different channel heights
- Patent number 9,960,257
- Issue date May 1, 2018
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming defect-free relaxed SiGe fins
- Patent number 9,882,052
- Issue date Jan 30, 2018
- GLOBALFOUNDRIES Inc.
- Robert Judson Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically insulated fin structure(s) with alternative channel ma...
- Patent number 9,881,830
- Issue date Jan 30, 2018
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical isolation of FinFET active region by selective oxidation...
- Patent number 9,716,174
- Issue date Jul 25, 2017
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin strain relaxed buffers with multilayer film stacks
- Patent number 9,679,972
- Issue date Jun 13, 2017
- GLOBALFOUNDRIES Inc.
- Jody Fronheiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Early PTS with buffer for channel doping control
- Patent number 9,647,086
- Issue date May 9, 2017
- GLOBALFOUNDRIES Inc.
- Steven Bentley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming low defect replacement fins for a FinFET semicon...
- Patent number 9,614,058
- Issue date Apr 4, 2017
- GLOBALFOUNDRIES Inc.
- Jody Fronheiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned dual-height isolation for bulk FinFET
- Patent number 9,564,486
- Issue date Feb 7, 2017
- International Business Machines Corporation
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming replacement fins for a FinFET device using a tar...
- Patent number 9,536,990
- Issue date Jan 3, 2017
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming embedded source/drain regions on finFET devices
- Patent number 9,530,869
- Issue date Dec 27, 2016
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming strained channel regions on FinFET devices by pe...
- Patent number 9,508,848
- Issue date Nov 29, 2016
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel cladding last process flow for forming a channel region on...
- Patent number 9,508,853
- Issue date Nov 29, 2016
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming strained channel regions on FinFET devices
- Patent number 9,502,507
- Issue date Nov 22, 2016
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET device including a uniform silicon alloy fin
- Patent number 9,478,663
- Issue date Oct 25, 2016
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming doped epitaxial SiGe material on semiconductor d...
- Patent number 9,455,140
- Issue date Sep 27, 2016
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET device including a uniform silicon alloy fin
- Patent number 9,406,803
- Issue date Aug 2, 2016
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel cladding last process flow for forming a channel region on...
- Patent number 9,362,405
- Issue date Jun 7, 2016
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming source/drain regions for a PMOS transistor devic...
- Patent number 9,343,300
- Issue date May 17, 2016
- GLOBALFOUNDRIES Inc.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Virtual relaxed substrate on edge-relaxed composite semiconductor p...
- Patent number 9,337,022
- Issue date May 10, 2016
- GLOBALFOUNDRIES Inc.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned dual-height isolation for bulk FinFET
- Patent number 9,324,790
- Issue date Apr 26, 2016
- International Business Machines Corporation
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CHANNEL UNIFORMITY HORIZONTAL GATE ALL AROUND DEVICE
- Publication number 20240136229
- Publication date Apr 25, 2024
- Applied Materials, Inc.
- Jody FRONHEISER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING STRAIN SiGe CHANNEL PMOS FOR GAA CMOS TECHNOLOGY
- Publication number 20240014214
- Publication date Jan 11, 2024
- Applied Materials, Inc.
- Sai Hooi Yeong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD-EFFECT TRANSISTORS WITH A GROWN SILICON-GERMANIUM CHANNEL
- Publication number 20200044029
- Publication date Feb 6, 2020
- GLOBALFOUNDRIES INC.
- George R. Mulfinger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD FOR REDUCED BIAS THRESHOLD INSTABILITY
- Publication number 20190363183
- Publication date Nov 28, 2019
- GENERAL ELECTRIC COMPANY
- Stephen Daley Arthur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS
- Publication number 20180226505
- Publication date Aug 9, 2018
- GLOBALFOUNDRIES INC.
- Jiseok KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MA...
- Publication number 20180138079
- Publication date May 17, 2018
- Murat Kerem AKARVARDAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING DEFECT-FREE RELAXED SiGe FINS
- Publication number 20180130656
- Publication date May 10, 2018
- GLOBALFOUNDRIES INC.
- Judson Robert Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE
- Publication number 20180083136
- Publication date Mar 22, 2018
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING DEFECT-FREE RELAXED SIGE FINS
- Publication number 20180006155
- Publication date Jan 4, 2018
- GLOBALFOUNDRIES INC.
- Robert Judson HOLT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE AREA AND SCHOTTKY BARRIER HEIGHT ENGINEERING FOR CONTACT TR...
- Publication number 20180006141
- Publication date Jan 4, 2018
- International Business Machines Corporation
- Jody Fronheiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING A SILICON BASED LAYER IN A TRENCH TO PREVENT CORNER ROUNDING
- Publication number 20180005826
- Publication date Jan 4, 2018
- GLOBALFOUNDRIES INC.
- Ajey P. JACOB
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SURFACE AREA AND SCHOTTKY BARRIER HEIGHT ENGINEERING FOR CONTACT TR...
- Publication number 20180006140
- Publication date Jan 4, 2018
- International Business Machines Corporation
- Jody Fronheiser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE HAVING SILICON GERMANIUM FINS AND METHOD OF...
- Publication number 20170179127
- Publication date Jun 22, 2017
- GLOBALFOUNDRIES INC.
- Judson R. Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EARLY PTS WITH BUFFER FOR CHANNEL DOPING CONTROL
- Publication number 20170047425
- Publication date Feb 16, 2017
- GLOBALFOUNDRIES INC.
- Steven BENTLEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING REPLACEMENT FINS COMPRISED OF MULTIPLE LAYERS OF...
- Publication number 20170033181
- Publication date Feb 2, 2017
- GLOBALFOUNDRIES INC.
- Timothy J. McArdle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING REPLACEMENT FINS FOR A FINFET DEVICE USING A TAR...
- Publication number 20160351681
- Publication date Dec 1, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERFACE PASSIVATION LAYERS AND METHODS OF FABRICATING
- Publication number 20160343806
- Publication date Nov 24, 2016
- GLOBALFOUNDRIES INC.
- Shariq SIDDIQUI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING EMBEDDED SOURCE/DRAIN REGIONS ON FINFET DEVICES
- Publication number 20160268399
- Publication date Sep 15, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem Akarvardar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMMON FABRICATION OF MULTIPLE FINFETs WITH DIFFERENT CHANNEL HEIGHTS
- Publication number 20160268400
- Publication date Sep 15, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem AKARVARDAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING FIN ISOLATION REGIONS UNDER TENSILE-STRAINED FIN...
- Publication number 20160225676
- Publication date Aug 4, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHANNEL CLADDING LAST PROCESS FLOW FOR FORMING A CHANNEL REGION ON...
- Publication number 20160204261
- Publication date Jul 14, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MA...
- Publication number 20160197004
- Publication date Jul 7, 2016
- GLOBALFOUNDRIES INC.
- Murat Kerem AKARVARDAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN
- Publication number 20160190323
- Publication date Jun 30, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEFECT-FREE STRAIN RELAXED BUFFER LAYER
- Publication number 20160190304
- Publication date Jun 30, 2016
- STMicroelectronics, Inc.
- Pierre MORIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHANNEL CLADDING LAST PROCESS FLOW FOR FORMING A CHANNEL REGION ON...
- Publication number 20160163863
- Publication date Jun 9, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN
- Publication number 20160126353
- Publication date May 5, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DOPED EPITAXIAL SiGe MATERIAL ON SEMICONDUCTOR D...
- Publication number 20160118251
- Publication date Apr 28, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING METASTABLE REPLACEMENT FINS FOR A FINFET SEMICON...
- Publication number 20160064250
- Publication date Mar 3, 2016
- GLOBALFOUNDRIES INC.
- Ajey P. Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RAISED SOURCE/DRAIN EPI WITH SUPPRESSED LATERAL EPI OVERGROWTH
- Publication number 20160056238
- Publication date Feb 25, 2016
- GLOBALFOUNDRIES INC.
- Kwan-Yong LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RETROGRADE DOPED LAYER FOR DEVICE ISOLATION
- Publication number 20160035728
- Publication date Feb 4, 2016
- GLOBALFOUNDRIES INC.
- Ajey Poovannummoottil Jacob
- H01 - BASIC ELECTRIC ELEMENTS

Jody A. Fronheiser

Person

Patents Grantslast 30 patents

Semiconductor device and method for reduced bias threshold instability

Field-effect transistors with a grown silicon-germanium channel

Surface area and Schottky barrier height engineering for contact tr...

Surface area and Schottky barrier height engineering for contact tr...

Semiconductor device and method for reduced bias threshold instability

Methods of forming a vertical transistor device

Vertical transport field effect transistors

Electrically insulated fin structure(s) with alternative channel ma...

Semiconductor integrated structure having an epitaxial SiGe layer e...

Methods of forming fin isolation regions under tensile-strained fin...

Common fabrication of multiple FinFETs with different channel heights

Forming defect-free relaxed SiGe fins

Electrically insulated fin structure(s) with alternative channel ma...

Electrical isolation of FinFET active region by selective oxidation...

Thin strain relaxed buffers with multilayer film stacks

Early PTS with buffer for channel doping control

Methods of forming low defect replacement fins for a FinFET semicon...

Self-aligned dual-height isolation for bulk FinFET

Methods of forming replacement fins for a FinFET device using a tar...

Methods of forming embedded source/drain regions on finFET devices

Methods of forming strained channel regions on FinFET devices by pe...

Channel cladding last process flow for forming a channel region on...

Methods of forming strained channel regions on FinFET devices

FinFET device including a uniform silicon alloy fin

Methods of forming doped epitaxial SiGe material on semiconductor d...

FinFET device including a uniform silicon alloy fin

Channel cladding last process flow for forming a channel region on...

Methods of forming source/drain regions for a PMOS transistor devic...

Virtual relaxed substrate on edge-relaxed composite semiconductor p...

Self-aligned dual-height isolation for bulk FinFET

Patents Applicationslast 30 patents

CHANNEL UNIFORMITY HORIZONTAL GATE ALL AROUND DEVICE

INTEGRATING STRAIN SiGe CHANNEL PMOS FOR GAA CMOS TECHNOLOGY

FIELD-EFFECT TRANSISTORS WITH A GROWN SILICON-GERMANIUM CHANNEL

SEMICONDUCTOR DEVICE AND METHOD FOR REDUCED BIAS THRESHOLD INSTABILITY

VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MA...

FORMING DEFECT-FREE RELAXED SiGe FINS

METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE

FORMING DEFECT-FREE RELAXED SIGE FINS

SURFACE AREA AND SCHOTTKY BARRIER HEIGHT ENGINEERING FOR CONTACT TR...

FORMING A SILICON BASED LAYER IN A TRENCH TO PREVENT CORNER ROUNDING

SURFACE AREA AND SCHOTTKY BARRIER HEIGHT ENGINEERING FOR CONTACT TR...

SEMICONDUCTOR STRUCTURE HAVING SILICON GERMANIUM FINS AND METHOD OF...

EARLY PTS WITH BUFFER FOR CHANNEL DOPING CONTROL

METHODS OF FORMING REPLACEMENT FINS COMPRISED OF MULTIPLE LAYERS OF...

METHODS OF FORMING REPLACEMENT FINS FOR A FINFET DEVICE USING A TAR...

INTERFACE PASSIVATION LAYERS AND METHODS OF FABRICATING

METHODS OF FORMING EMBEDDED SOURCE/DRAIN REGIONS ON FINFET DEVICES

COMMON FABRICATION OF MULTIPLE FINFETs WITH DIFFERENT CHANNEL HEIGHTS

METHODS OF FORMING FIN ISOLATION REGIONS UNDER TENSILE-STRAINED FIN...

CHANNEL CLADDING LAST PROCESS FLOW FOR FORMING A CHANNEL REGION ON...

ELECTRICALLY INSULATED FIN STRUCTURE(S) WITH ALTERNATIVE CHANNEL MA...

FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN

DEFECT-FREE STRAIN RELAXED BUFFER LAYER

CHANNEL CLADDING LAST PROCESS FLOW FOR FORMING A CHANNEL REGION ON...

FINFET DEVICE INCLUDING A UNIFORM SILICON ALLOY FIN

METHODS OF FORMING DOPED EPITAXIAL SiGe MATERIAL ON SEMICONDUCTOR D...

METHODS OF FORMING METASTABLE REPLACEMENT FINS FOR A FINFET SEMICON...

RAISED SOURCE/DRAIN EPI WITH SUPPRESSED LATERAL EPI OVERGROWTH

RETROGRADE DOPED LAYER FOR DEVICE ISOLATION