Patent Application
20170033181
1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming replacement fins comprised of multiple layers of different semiconductor materials and the resulting FinFET device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A conventional FET is a planar device that typically includes a source region, a drain region and a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed and in lowering operation currents and voltages of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure.
In the FinFET device 10, the gate structure 16 encloses (or is positioned around) both of the side surfaces and the upper surface of all or a portion of the fins 14 to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fins 14 and the FinFET device only has a dual-gate structure (sidewalls only). Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to increase the drive current per footprint of the device. Also, in a FinFET, the improved gate control through multiple gates on a narrow, fully-depleted semiconductor fin significantly reduces the short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins 14, i.e., the vertically oriented sidewalls and the top upper surface of the fin, form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device with a single fin, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance, capability and reliability of such devices. Device designers are currently investigating using alternative semiconductor materials, such as so-called SiGe, Ge and III-V materials, to manufacture FinFET devices which are intended to enhance the performance capabilities of such devices, e.g., to enable low-voltage operation without degrading their operating speed.
However, the integration of such alternative materials on silicon substrates (the dominant substrates used in the industry) is non-trivial due to, among other issues, the large difference in lattice constants between such alternative materials and silicon. That is, with reference to
With respect to forming such lattice-mismatched materials on one another, there is a concept that is generally referred to as the “critical thickness” (“CT”) of a material. The term “critical thickness” generally refers to materials that are in one of three conditions, i.e., so-called “stable,” “metastable” or “relaxed-with-defects” conditions. These three conditions also generally reflect the state of the strain on the material. That is, a stable material is in a fully-strained condition that is 100% strained in at least one crystalline plane of the material.
With reference to
The presence of defects in an alternative material fin structure would be detrimental to device operations. One process that has been investigated for use in forming such alternative fin materials is known as aspect-ratio-trapping (ART). In general, the ART process involves forming a masking layer, such as silicon dioxide, above a semiconductor substrate, such as silicon, patterning the masking layer to define a trench that exposes the underlying substrate, and performing an epitaxial growth process to form an alternative fin material, e.g., silicon-germanium, on the exposed substrate, wherein the growth is confined within the trench. That is, the ART process involves epitaxially growing fully relaxed, unstrained material hetero-structures in a high aspect-ratio silicon dioxide trench having an aspect ratio of 5 or greater in an attempt to decrease defects. In some applications, the ART process may involve the formation of trenches that have a very high aspect ratio, e.g., about 25-30. Importantly, in the ART process, the trench is made deep enough such that defects generated in the alternative fin material will be trapped at or near the bottom of the original trench and in the sidewalls of the trench positioned slightly above the interface between the substrate material and the alternative fin material. The amount of defects generated and the propagation of such defects will depend upon the crystal orientation of the substrate. The intent of the ART process is that, while the defect-containing fin material is present at or near the bottom of the trench, the upper-most portions of the epitaxially grown alternative fin material will be substantially defect-free material but, importantly, it is an un-strained material. That is, the alternative fin material is fully relaxed in all crystalline planes, e.g., in the crystalline planes that correspond to the axial length direction, height direction and width direction of the fin. This occurs due to the “trapping” of the defects at or near the bottom of the trench, with the result being the formation of substantially defect-free alternative fin material above the defective-containing portions of the alternative fin material in the lower portion of the trench. In principle, the ART process does not present a limitation with respect to the thickness of the lattice-mismatched layer, which is typically fully relaxed, a few 100 nm thick, and with defects intentionally confined close to the bottom interface. The defects are generated along the (111) crystallographic direction of the alternative fin material and they are captured or stopped by the sidewalls of the trench.
In one particular example, as it relates to the formation of P-type FinFET devices, device designers have investigated the use of pure germanium and silicon-germanium, along with a high uniaxial compressive stress, as the fin material so as to improve charge carrier (i.e., holes) mobility in the devices. To be effective, the germanium or silicon-germanium fin material will ideally be formed in a highly-strained, substantially defect-free condition. Several prior art techniques have been attempted in an effort to form such materials, e.g., blanket growth of a germanium or silicon-germanium material on a stress relaxation buffer layer having an intermediate lattice constant between the fin material and the silicon substrate, cladding processes, cladding plus condensation thermal treatment, replacement fin techniques, etc. Unfortunately, the prior art techniques have yet to be able to form highly-strained, substantially defect-free germanium or silicon-germanium in a sufficient thickness so that it may be used in actual devices. In addition, many of the above-mentioned prior art processing techniques are generally incompatible in terms of the thermal budget required to practice the conventional Si baseline integration flows on bulk substrate materials.
The present disclosure is directed to various methods of forming replacement fins comprised of multiple layers of different semiconductor materials and the resulting FinFET device that may solve or reduce one or more of the problems identified above.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods of forming replacement fins comprised of multiple layers of different semiconductor materials and the resulting FinFET device. One illustrative method disclosed herein includes, among other things, forming a substrate fin, forming a layer of insulating material in a plurality of trenches adjacent the substrate fin, and performing a fin recess etching process to remove a portion of the substrate fin and define a recessed substrate fin and a substrate fin cavity in the layer of insulating material above the recessed substrate fin. In this example, the method further includes individually forming alternating layers of different semiconductor materials in the substrate fin cavity so as to form a multi-layer fin above the recessed substrate fin, wherein each of the layers of different semiconductor materials is formed to a final thickness that is less than a critical thickness of a layer of different semiconductor material being formed, recessing the layer of insulating material so as to expose at least a portion of the multi-layer fin above a recessed upper surface of the layer of insulating material and forming a gate structure around at least a portion of the exposed multi-layer fin.
Yet another illustrative method disclosed herein includes, among other things, forming a layer of insulating material in a plurality of trenches adjacent a substrate fin, and performing a fin recess etching process to remove a portion of the substrate fin so as to define a recessed substrate fin and a substrate fin cavity in the layer of insulating material above the recessed substrate fin. In this embodiment, the method also includes individually forming layers of semiconductor materials in the substrate fin cavity so as to form a multi-layer fin above the recessed substrate fin by performing the following actions: individually forming a first layer of silicon-germanium (SixGe1-x), where x ranges from 0 to 0.95, on and in contact with the recessed substrate fin, wherein the first layer of silicon-germanium is formed to a first final thickness that is less than a critical thickness of the first layer of silicon-germanium; individually forming a first layer of silicon on and in contact with the first layer of silicon-germanium (SixGe1-x), wherein the first layer of silicon is formed to a second final thickness that is less than a critical thickness of the first layer of silicon; individually forming a second layer of silicon-germanium (SixGe1-x), where x ranges from 0 to 0.95, on and in contact with first layer of silicon, wherein the second layer of silicon-germanium is formed to a third final thickness that is less than a critical thickness of the second layer of silicon-germanium; and individually forming a second layer of silicon on and in contact with the second layer of silicon-germanium (SixGe1-x), wherein the second layer of silicon is formed to a fourth final thickness that is less than a critical thickness of the second layer of silicon-germanium. In this example, the method also includes recessing the layer of insulating material so as to expose at least a portion of the multi-layer fin above a recessed upper surface of the layer of insulating material and forming a gate structure around at least a portion of the multi-layer fin.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various methods of forming replacement fins comprised of multiple layers of different semiconductor materials and the resulting FinFET device. The methods disclosed herein may be employed in manufacturing either an N-type device or a P-type device, and the gate structure of such devices may be formed using either so-called “gate-first” or “replacement gate” (“gate-last” or “gate-metal-last”) techniques. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc., and the methods disclosed herein may be employed to form N-type or P-type semiconductor devices. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
In the attached drawings, the device 100 is depicted as being formed above a semiconductor substrate 102 comprised of a semiconductor material, such as, for example, a bulk silicon substrate. Thus, the terms “substrate,” “semiconductor substrate” or “semiconducting substrate” should be understood to cover all semiconductor materials. An isolation material (not shown) may be formed in the substrate 102 to define illustrative spaced-apart active regions in the substrate 102. The isolation regions may be formed using traditional techniques, e.g., traditional shallow trench isolation regions may be formed in the substrate 102. In the case of the illustrative FinFET devices disclosed herein, the isolation regions may be formed before or after the formation of the fin structures that will be formed as described more fully below.
The width and height of the substrate fin structure 106, as well as the overall size, shape and configuration of the fin-formation trenches 102X may vary depending on the particular application. In one illustrative embodiment, based on current day technology, the height 106H of the substrate fin 106 (i.e., the depth the trenches 102X) may range from approximately 5-200 nm and the lateral width of the substrate fin 106 may be about 20-30 nm or less.
In the illustrative examples depicted in the attached drawings, the substrate fin 106 and the fin-formation trenches 102X are depicted as having a uniform and generally rectangular configuration. In the attached figures, the fin-formation trenches 102X are depicted as having been formed by performing an anisotropic etching process that results in the fin-formation trenches 102X having a schematically depicted, generally rectangular configuration. In an actual real-world device, the sidewalls of the fin-formation trenches 102X may be somewhat inwardly tapered, although that configuration is not depicted in the attached drawings. As a result, the sidewalls of the substrate fin 106 may also be tapered, much like the sidewall of the fin shown in
The first layer of semiconductor material 110A may be formed using two different techniques such that it has the desired final thickness 110T. In one embodiment, as shown in
In another embodiment, as shown in
As with the first layer of semiconductor material 110A, the second layer of semiconductor material 114A may be formed using two different techniques such that it has the desired final thickness 114T. In one embodiment, as shown in
In another embodiment, as shown in
At the point of processing depicted in
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
