Patent Application
20180005826
The present disclosure relates to the manufacture of semiconductor devices, such as integrated circuits (ICs). The present disclosure is particularly applicable to forming alternate channel FIN field effect transistors (FINFETs), particularly for the 14 nanometer (nm) technology node and beyond.
Conventional processes for the fabrication of semiconductor devices often incorporate a lithographic process to create a desired pattern on a Si substrate. As the critical dimensions of the desired pattern shrink, the consistency between the masked and actual layout pattern developed in the photoresist on the Si substrate is significantly reduced. Proximity effects in a lithographic process can arise during exposure, resist pattern formation and subsequent pattern transfer steps, such as etching. The proximity effect causes corner rounding, where substantially square corners of a pattern are rounded. Corner rounding generates many side effects, such as unexpected pattern shapes that may cause layout errors and device performance issues such as short-circuits, open-circuits, RC variation, and device performance drift, which in turn significantly impact device performance, quality and reliability.
For example,
A need therefore exists for methodology enabling formation of a SiGe layer on silicon to form a SiGe FINFET transistor with no corner rounding and the resulting device.
An aspect of the present disclosure is a method including forming a Si based layer in a trench prior to forming a SiGe layer to prevent corner rounding for the SiGe layer.
Another aspect of the present disclosure is a device including a Si based layer with a flat upper surface under a SiGe layer in a trench to prevent corner rounding of the SiGe layer.
Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
According to the present disclosure, some technical effects may be achieved in part by a method of including: providing a Si substrate; forming a trench in the Si substrate; forming a Si based layer with a flat upper surface in the trench; and forming a SiGe layer over the Si based layer.
Another aspect includes forming the trench by RIE. Further aspects include forming the Si based layer and the SiGe layer by epitaxially growing a lattice compliant Si layer and the SiGe layer in the trench. Other aspects include forming the Si based layer and the SiGe layer by epitaxially growing first and second SiGe layers, the first SiGe layer having a lower germanium (Ge) concentration than the second SiGe layer. Further aspects include forming the trench to a depth of 100 nm to 500 nm. Additional aspects include forming the Si based layer to a thickness equal to a difference between a depth of the trench and a thickness of the SiGe layer. Other aspects include forming the SiGe layer to a thickness of 10 nm to 60 nm. Further aspects include epitaxial (EPI) pre-baking surfaces of the trench subsequent to etching. Another aspect includes EPI pre-baking surfaces of the trench at a temperature of 750° C. to 1200° C. and a pressure of 10 torr to 600 torr for 1 minute to 5 minutes. A further aspect includes counter doping the lattice compliant Si layer with an n-type dopant.
A further aspect of the present disclosure is a device including: a Si substrate; a trench formed in the Si substrate; a Si based layer with a flat upper surface formed in the trench; and a SiGe layer with no corner rounding formed over the Si based layer.
Aspects include the Si based layer including a lattice compliant layer. Other aspects include the Si based layer including a second SiGe layer with a Ge concentration lower than the concentration of the SiGe layer. A further aspect includes the trench having a depth of 100 nm to 500 nm. Another aspect includes the Si based layer having a thickness equal to a difference between a depth of the trench and a thickness of the SiGe layer. A further aspect includes the SiGe layer having a thickness of 10 nm to 60 nm.
Another aspect of the present disclosure is a method including: providing a Si substrate; etching a trench to a depth of 100 nm to 500 nm in the Si substrate by RIE; epitaxially growing a Si based layer with a flat upper surface in the trench; and epitaxially growing a SiGe layer with no corner rounding over the Si based layer.
Aspects include the Si based layer including a lattice compliant Si layer. Another aspect includes the Si based layer including a second SiGe layer having a lower Ge concentration than the SiGe layer. Other aspects include forming the lattice compliant Si layer to a thickness of equal to a difference between a depth of the trench and a thickness of the SiGe layer and forming the SiGe layer to a thickness of 10 nm to 60nm.
Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
The present disclosure addresses and solves the current problem of corner rounding attendant upon forming a trench in a Si substrate for an alternate channel FINFET. In accordance with embodiments of the present disclosure, a deeper trench is formed and a Si based layer is formed in the trench until a flat upper surface is achieved, prior to epitaxially growing the SiGe layer (over the Si based layer).
Methodology in accordance with embodiments of the present disclosure includes providing a Si substrate and forming a trench in the Si substrate. Then, a Si based layer with a flat upper surface is formed in the trench. Next, a SiGe layer is formed over the Si based layer.
Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
In
Alternatively, as illustrated in
Alternatively, if the SiGe layer 207 has a high concentration of germanium (Ge), for example higher than 40%, e.g. 70%, the Si based layer 205 may be a SiGe layer with a low concentration of Ge, for example 5 to 40%. Layers 205 and 207 are chosen so that the second layer maintains stress. Further, the temperature and pressure of the second layer should be less than that of the first layer or within a range where the reflow of the first layer does not occur inside the trench creating a convex trench.
In addition, the Si based layer 205 may include super steep retrograde well (SSRW) type doping. More specifically, SSRW dopants include phosphorous (P) or arsenic (As), with carbon layers that prevent diffusion of the dopants.
The embodiments of the present disclosure can achieve several technical effects, such as an improved device performance, maintaining good gate oxide integrity and a reduced junction leakage. Devices formed in accordance with embodiments of the present disclosure enjoy utility in various industrial applications, e.g., microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated FINFET semiconductor devices, particularly for the 14 nm technology node and beyond.
In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.
