John B. Dillon

Person

Washington, VA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transceiver with latency alignment circuitry
- Patent number 8,458,426
- Issue date Jun 4, 2013
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip socket assembly and chip file assembly for semiconductor chips
- Patent number 8,096,812
- Issue date Jan 17, 2012
- Rambus Inc.
- Donald V. Perino
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Transceiver with latency alignment circuitry
- Patent number 8,086,812
- Issue date Dec 27, 2011
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Current control technique
- Patent number 7,352,234
- Issue date Apr 1, 2008
- Rambus Inc.
- Billy Wayne Garrett, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for pipelined memory operations
- Patent number 7,353,357
- Issue date Apr 1, 2008
- Rambus Inc.
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for pipelined memory operations
- Patent number 7,330,951
- Issue date Feb 12, 2008
- Rambus Inc.
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of controlling a memory device having a memory core
- Patent number 7,287,109
- Issue date Oct 23, 2007
- Rambus Inc.
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device having an adjustable voltage swing setting
- Patent number 7,167,039
- Issue date Jan 23, 2007
- Rambus Inc.
- Billy Wayne Garrett, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transceiver with latency alignment circuitry
- Patent number 7,124,270
- Issue date Oct 17, 2006
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Connector with integral transmission line bus
- Patent number RE39153
- Issue date Jul 4, 2006
- Rambus Inc.
- Donald V. Perino
- 439 - Electrical connectors
Information Patent Grant
Transceiver with latency alignment circuitry
- Patent number 7,065,622
- Issue date Jun 20, 2006
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transceiver with latency alignment circuitry
- Patent number 7,010,658
- Issue date Mar 7, 2006
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of operation in a system having a memory device having an ad...
- Patent number 6,975,159
- Issue date Dec 13, 2005
- Rambus Inc.
- Billy Wayne Garrett, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System including an integrated circuit memory device having an adju...
- Patent number 6,975,160
- Issue date Dec 13, 2005
- Rambus Inc.
- Billy Wayne Garrett, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for pipelined memory operations
- Patent number 6,963,956
- Issue date Nov 8, 2005
- Rambus Inc.
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory integrated circuit device which samples data upon detection...
- Patent number 6,931,467
- Issue date Aug 16, 2005
- Rambus Inc.
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system including a memory device having a controlled output...
- Patent number 6,870,419
- Issue date Mar 22, 2005
- Rambus Inc.
- Billy Wayne Garrett, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Protocol for communication with dynamic memory
- Patent number 6,810,449
- Issue date Oct 26, 2004
- Rambus, Inc.
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for pipelined memory operations
- Patent number 6,718,431
- Issue date Apr 6, 2004
- Rambus Inc.
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transceiver with latency alignment circuitry
- Patent number 6,643,752
- Issue date Nov 4, 2003
- Rambus Inc.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip socket assembly and chip file assembly for semiconductor chips
- Patent number 6,619,973
- Issue date Sep 16, 2003
- Rambus, Inc.
- Donald V. Perino
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory system including a memory device having a controlled output...
- Patent number 6,608,507
- Issue date Aug 19, 2003
- Rambus Inc.
- Billy Wayne Garrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for synchronizing a control signal
- Patent number 6,594,326
- Issue date Jul 15, 2003
- Rambus Inc.
- Clemenz Portmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip socket assembly and chip file assembly for semiconductor chips
- Patent number 6,589,059
- Issue date Jul 8, 2003
- Rambus, Inc.
- Donald V. Perino
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Protocol for communication with dynamic memory
- Patent number 6,591,353
- Issue date Jul 8, 2003
- Rambus Inc.
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor controller device having a controlled output driver c...
- Patent number 6,556,052
- Issue date Apr 29, 2003
- Billy Wayne Garrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for multilevel signaling
- Patent number 6,504,875
- Issue date Jan 7, 2003
- Rambus Inc.
- Donald V. Perino
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Protocol for communication with dynamic memory
- Patent number 6,470,405
- Issue date Oct 22, 2002
- Rambus Inc.
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device having a controlled output driver chara...
- Patent number 6,462,591
- Issue date Oct 8, 2002
- Rambus Inc.
- Billy Wayne Garrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Socket for coupling an integrated circuit package to a printed circ...
- Patent number 6,447,321
- Issue date Sep 10, 2002
- Rambus, Inc.
- Donald V. Perino
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT DEVICE COMPRISES AN INTERFACE TO TRANSMIT A FIRS...
- Publication number 20120201089
- Publication date Aug 9, 2012
- RAMBUS INC.
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Controlling A Memory Device Having a Memory Core
- Publication number 20080043546
- Publication date Feb 21, 2008
- RAMBUS INC.
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method for Pipelined Memory Operations
- Publication number 20070140035
- Publication date Jun 21, 2007
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY
- Publication number 20070118711
- Publication date May 24, 2007
- RAMBUS INC.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CURRENT CONTROL TECHNIQUE
- Publication number 20070115043
- Publication date May 24, 2007
- RAMBUS INC.
- Billy Wayne Garrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY
- Publication number 20070011426
- Publication date Jan 11, 2007
- RAMBUS INC.
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for pipelined memory operations
- Publication number 20060059299
- Publication date Mar 16, 2006
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chip socket assembly and chip file assembly for semiconductor chips
- Publication number 20060014402
- Publication date Jan 19, 2006
- Donald V. Perino
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Transceiver with latency alignment circuitry
- Publication number 20050160247
- Publication date Jul 21, 2005
- John B. Dillon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transceiver with latency alignment circuitry
- Publication number 20050149685
- Publication date Jul 7, 2005
- Kevin Donnelly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System including an integrated circuit memory device having an adju...
- Publication number 20050099218
- Publication date May 12, 2005
- Billy Wayne Garrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of operation in a system having a memory device having an ad...
- Publication number 20050083104
- Publication date Apr 21, 2005
- Billy Wayne Garrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Protocol for communication with dynamic memory
- Publication number 20050066114
- Publication date Mar 24, 2005
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory device having an adjustable voltage swing setting
- Publication number 20050040878
- Publication date Feb 24, 2005
- Billy Wayne Garrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for pipelined memory operations
- Publication number 20040193788
- Publication date Sep 30, 2004
- Rambus Inc.
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory system including a memory device having a controlled output...
- Publication number 20020196059
- Publication date Dec 26, 2002
- Billy Wayne Garrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus for multilevel signaling
- Publication number 20020186777
- Publication date Dec 12, 2002
- Donald V. Perino
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Apparatus and method for pipelined memory operations
- Publication number 20020095560
- Publication date Jul 18, 2002
- Richard M. Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory integrated circuit device which samples data upon detection...
- Publication number 20020087790
- Publication date Jul 4, 2002
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor controller device having a controlled output driver c...
- Publication number 20020070771
- Publication date Jun 13, 2002
- Billy Wayne Garrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chip socket assembly and chip file assembly for semiconductor chips
- Publication number 20020055285
- Publication date May 9, 2002
- Rambus, Inc.
- Donald V. Perino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip socket assembly and chip file assembly for semiconductor chips
- Publication number 20020031923
- Publication date Mar 14, 2002
- Donald V. Perino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor memory device having a controlled output driver chara...
- Publication number 20020017929
- Publication date Feb 14, 2002
- Billy Wayne Garrett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chip socket assembly and chip file assembly for semiconductor chips
- Publication number 20020016091
- Publication date Feb 7, 2002
- Rambus, Inc.
- Donald V. Perino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Protocol for communication with dynamic memory
- Publication number 20020004865
- Publication date Jan 10, 2002
- Richard Maurice Barth
- G06 - COMPUTING CALCULATING COUNTING

John B. Dillon

Person

Patents Grantslast 30 patents

Transceiver with latency alignment circuitry

Chip socket assembly and chip file assembly for semiconductor chips

Transceiver with latency alignment circuitry

Current control technique

Apparatus and method for pipelined memory operations

Apparatus and method for pipelined memory operations

Method of controlling a memory device having a memory core

Memory device having an adjustable voltage swing setting

Transceiver with latency alignment circuitry

Connector with integral transmission line bus

Transceiver with latency alignment circuitry

Transceiver with latency alignment circuitry

Method of operation in a system having a memory device having an ad...

System including an integrated circuit memory device having an adju...

Apparatus and method for pipelined memory operations

Memory integrated circuit device which samples data upon detection...

Memory system including a memory device having a controlled output...

Protocol for communication with dynamic memory

Apparatus and method for pipelined memory operations

Transceiver with latency alignment circuitry

Chip socket assembly and chip file assembly for semiconductor chips

Memory system including a memory device having a controlled output...

Apparatus and method for synchronizing a control signal

Chip socket assembly and chip file assembly for semiconductor chips

Protocol for communication with dynamic memory

Semiconductor controller device having a controlled output driver c...

Apparatus for multilevel signaling

Protocol for communication with dynamic memory

Semiconductor memory device having a controlled output driver chara...

Socket for coupling an integrated circuit package to a printed circ...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT DEVICE COMPRISES AN INTERFACE TO TRANSMIT A FIRS...

Method of Controlling A Memory Device Having a Memory Core

Apparatus and Method for Pipelined Memory Operations

TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY

CURRENT CONTROL TECHNIQUE

TRANSCEIVER WITH LATENCY ALIGNMENT CIRCUITRY

Apparatus and method for pipelined memory operations

Chip socket assembly and chip file assembly for semiconductor chips

Transceiver with latency alignment circuitry

Transceiver with latency alignment circuitry

System including an integrated circuit memory device having an adju...

Method of operation in a system having a memory device having an ad...

Protocol for communication with dynamic memory

Memory device having an adjustable voltage swing setting

Apparatus and method for pipelined memory operations

Memory system including a memory device having a controlled output...

Apparatus for multilevel signaling

Apparatus and method for pipelined memory operations

Memory integrated circuit device which samples data upon detection...

Semiconductor controller device having a controlled output driver c...

Chip socket assembly and chip file assembly for semiconductor chips

Chip socket assembly and chip file assembly for semiconductor chips

Semiconductor memory device having a controlled output driver chara...

Chip socket assembly and chip file assembly for semiconductor chips

Protocol for communication with dynamic memory