John Millard Caywood

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for determining fault sources for device failures
- Patent number 6,920,596
- Issue date Jul 19, 2005
- Heuristics Physics Laboratories, Inc.
- Arman Sagatelian
- G01 - MEASURING TESTING
Information Patent Grant
Correction of overlay offset between inspection layers
- Patent number 6,780,656
- Issue date Aug 24, 2004
- HPL Technologies, Inc.
- David Muradian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for selecting an optimal level of redundancy in the design o...
- Patent number 6,745,370
- Issue date Jun 1, 2004
- Heuristics Physics Laboratories, Inc.
- Julie Segal
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage single supply CMOS electrically erasable read-only memory
- Patent number 6,574,140
- Issue date Jun 3, 2003
- The John Millard and Pamela Ann Caywood 1989 Revocable Living Trust
- John M. Caywood
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for injecting charge onto the floating gate of...
- Patent number 6,534,816
- Issue date Mar 18, 2003
- John Caywood
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for injecting charge onto the floating gate of...
- Patent number 6,479,863
- Issue date Nov 12, 2002
- John M. Caywood
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming an EEPROM cell together with transistor for peri...
- Patent number 6,451,652
- Issue date Sep 17, 2002
- The John Millard and Pamela Ann Caywood 1989 Revocable Living Trust
- John Caywood
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile latch
- Patent number 6,411,545
- Issue date Jun 25, 2002
- John Millard and Pamela Ann Caywood 1989 Revokable Living Trust
- John Caywood
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for injecting charge onto the floating gate of...
- Patent number 6,384,451
- Issue date May 7, 2002
- John M. Caywood
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low voltage single CMOS electrically erasable read-only memory
- Patent number 6,201,732
- Issue date Mar 13, 2001
- John M. Caywood
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for using inspection data for improving throughput of steppe...
- Patent number 6,096,093
- Issue date Aug 1, 2000
- Heuristic Physics Laboratories
- John Caywood
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Timing delay generator and method including compensation for enviro...
- Patent number 6,092,030
- Issue date Jul 18, 2000
- Credence Systems Corporation
- Yervant D. Lepejian
- G01 - MEASURING TESTING
Information Patent Grant
Low voltage single CMOS electrically erasable read-only memory
- Patent number 5,986,931
- Issue date Nov 16, 1999
- John M. Caywood
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient built-in self test for embedded memories with differing a...
- Patent number 5,974,579
- Issue date Oct 26, 1999
- Credence Systems Corporation
- Yervant David Lepejian
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage single supply CMOS electrically erasable read-only memory
- Patent number 5,790,455
- Issue date Aug 4, 1998
- Caywood; John
- John M. Caywood
- G11 - INFORMATION STORAGE
Information Patent Grant
General purpose, non-volatile reprogrammable switch
- Patent number 5,764,096
- Issue date Jun 9, 1998
- Gatefield Corporation
- Robert J. Lipp
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for programming flash EEPROM devices
- Patent number 5,621,738
- Issue date Apr 15, 1997
- Eastman Kodak Company
- John Caywood
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic failure analysis system
- Patent number 5,475,695
- Issue date Dec 12, 1995
- Semiconductor Diagnosis & Test Corporation
- John M. Caywood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sector erasable flash EEPROM
- Patent number 5,270,980
- Issue date Dec 14, 1993
- Eastman Kodak Company
- Jagdish Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash EPROM cell and method for operating same
- Patent number 5,235,544
- Issue date Aug 10, 1993
- Caywood; John
- John Caywood
- G11 - INFORMATION STORAGE
Information Patent Grant
Field-programmable redundancy apparatus for memory arrays
- Patent number 5,161,157
- Issue date Nov 3, 1992
- Xicor, Inc.
- William H. Owen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field-programmable redundancy apparatus for memory arrays
- Patent number 5,153,880
- Issue date Oct 6, 1992
- Xicor, Inc.
- William H. Owen
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile associative memory system
- Patent number 5,070,480
- Issue date Dec 3, 1991
- John M. Caywood
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power random access memory with self-refreshing cells
- Patent number 4,122,550
- Issue date Oct 24, 1978
- Intel Corporation
- John M. Caywood
- G11 - INFORMATION STORAGE
Information Patent Grant
Read only memory utilizing charge coupled device structures
- Patent number 4,072,977
- Issue date Feb 7, 1978
- Texas Instruments Incorporated
- Robert T. Bate
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge transfer device signal processing
- Patent number 3,944,849
- Issue date Mar 16, 1976
- Texas Instruments Inc.
- Al Felix Tasch
- G11 - INFORMATION STORAGE
Information Patent Grant
Three level electrode configuration for three phase charge coupled...
- Patent number 3,943,543
- Issue date Mar 9, 1976
- Texas Instruments Incorporated
- John Millard Caywood
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic shutter for a charge-coupled imager
- Patent number 3,934,161
- Issue date Jan 20, 1976
- Texas Instruments Incorporated
- John Millard Caywood
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for injecting charge onto the floating gate of...
- Publication number 20040021170
- Publication date Feb 5, 2004
- John M. Caywood
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Correction of overlay offset between inspection layers
- Publication number 20030160627
- Publication date Aug 28, 2003
- HPL Technologies, Inc.
- David Muradian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for determining fault sources for device failures
- Publication number 20030140294
- Publication date Jul 24, 2003
- Arman Sagatelian
- G01 - MEASURING TESTING
Information Patent Application
Low voltage single supply cmos electrically erasable read-only memory
- Publication number 20020191439
- Publication date Dec 19, 2002
- John M. Caywood
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for injecting charge onto the floating gate of...
- Publication number 20010019151
- Publication date Sep 6, 2001
- John M. Caywood
- H01 - BASIC ELECTRIC ELEMENTS

John Millard Caywood

Person

Patents Grantslast 30 patents

Method and apparatus for determining fault sources for device failures

Correction of overlay offset between inspection layers

Method for selecting an optimal level of redundancy in the design o...

Low voltage single supply CMOS electrically erasable read-only memory

Method and apparatus for injecting charge onto the floating gate of...

Method and apparatus for injecting charge onto the floating gate of...

Method for forming an EEPROM cell together with transistor for peri...

Non-volatile latch

Method and apparatus for injecting charge onto the floating gate of...

Low voltage single CMOS electrically erasable read-only memory

Method for using inspection data for improving throughput of steppe...

Timing delay generator and method including compensation for enviro...

Low voltage single CMOS electrically erasable read-only memory

Efficient built-in self test for embedded memories with differing a...

Low voltage single supply CMOS electrically erasable read-only memory

General purpose, non-volatile reprogrammable switch

Method for programming flash EEPROM devices

Automatic failure analysis system

Sector erasable flash EEPROM

Flash EPROM cell and method for operating same

Field-programmable redundancy apparatus for memory arrays

Field-programmable redundancy apparatus for memory arrays

Nonvolatile associative memory system

Low power random access memory with self-refreshing cells

Read only memory utilizing charge coupled device structures

Charge transfer device signal processing

Three level electrode configuration for three phase charge coupled...

Electronic shutter for a charge-coupled imager

Patents Applicationslast 30 patents

Method and apparatus for injecting charge onto the floating gate of...

Correction of overlay offset between inspection layers

Method and apparatus for determining fault sources for device failures

Low voltage single supply cmos electrically erasable read-only memory

Method and apparatus for injecting charge onto the floating gate of...