Jon C. Cheek

Person

Round Rock, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Embedded NVM in a HKMG process
- Patent number 9,276,008
- Issue date Mar 1, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Jon D. Cheek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded NVM in a HKMG process
- Patent number 9,054,220
- Issue date Jun 9, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Jon D. Cheek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of making semiconductor device comp...
- Patent number 7,422,956
- Issue date Sep 9, 2008
- Advanced Micro Devices, Inc.
- Andrew Michael Waite
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methodology to reduce SOI floating-body effect
- Patent number 7,410,876
- Issue date Aug 12, 2008
- FREESCALE SEMICONDUCTOR, INC.
- Byoung W. Min
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-power multiple-channel fully depleted quantum well CMOSFETs
- Patent number 7,253,484
- Issue date Aug 7, 2007
- Advanced Micro Devices, Inc.
- James N. Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interlayer dielectric under stress for an integrated circuit
- Patent number 7,238,990
- Issue date Jul 3, 2007
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-on-insulator semiconductor device with silicon layers havin...
- Patent number 7,235,433
- Issue date Jun 26, 2007
- Advanced Micro Devices, Inc.
- Andrew M. Waite
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor component
- Patent number 7,208,383
- Issue date Apr 24, 2007
- Advanced Micro Devices, Inc.
- Chad Weintraub
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for offsetting a silicide process from a gate electrode of a...
- Patent number 7,179,745
- Issue date Feb 20, 2007
- Advanced Micro Devices, Inc.
- Andrew M. Waite
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of reducing STI divot formation during semiconductor device...
- Patent number 7,091,106
- Issue date Aug 15, 2006
- Advanced Micro Devices, Inc.
- Douglas J. Bonser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-power multiple-channel fully depleted quantum well CMOSFETs
- Patent number 7,074,657
- Issue date Jul 11, 2006
- Advanced Micro Devices, Inc.
- James N. Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor component having an early...
- Patent number 6,833,307
- Issue date Dec 21, 2004
- Advanced Micro Devices, Inc.
- Derick Wristers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming silicide layers over a plurality of semiconductor...
- Patent number 6,787,464
- Issue date Sep 7, 2004
- Advanced Micro Devices, Inc.
- Jon D. Cheek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming source/drain regions in a semiconductor device
- Patent number 6,720,227
- Issue date Apr 13, 2004
- Advanced Micro Devices, Inc.
- Daniel Kadosh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure having elevated salicided source/drain regi...
- Patent number 6,674,135
- Issue date Jan 6, 2004
- Advanced Micro Devices, Inc.
- Jon Cheek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure having a metal gate electrode and elevated...
- Patent number 6,638,829
- Issue date Oct 28, 2003
- Advanced Micro Devices, Inc.
- Jon Cheek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor device having an enhanced width dimension and a method o...
- Patent number 6,580,122
- Issue date Jun 17, 2003
- Advanced Micro Devices, Inc.
- Derick J. Wristers
- G01 - MEASURING TESTING
Information Patent Grant
Self-aligned VT implant
- Patent number 6,566,696
- Issue date May 20, 2003
- Advanced Micro Devices, Inc.
- Jon D. Cheek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making transistors with gate insulation layers of differi...
- Patent number 6,541,321
- Issue date Apr 1, 2003
- Advanced Micro Devices, Inc.
- James F. Buller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Removable spacer technique
- Patent number 6,506,642
- Issue date Jan 14, 2003
- Advanced Micro Devices, Inc.
- Scott D. Luning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of analyzing the effects of shadowing of angled halo implants
- Patent number 6,426,262
- Issue date Jul 30, 2002
- Advanced Micro Devices, Inc.
- Mark Brandon Fuselier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density memory cell assembly and methods
- Patent number 6,417,539
- Issue date Jul 9, 2002
- Advanced Micro Devices, Inc.
- Mark I. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of controlling junction recesses in a semiconductor device
- Patent number 6,406,964
- Issue date Jun 18, 2002
- Advanced Micro Devices, Inc.
- Derick J. Wristers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure for measuring effective channel length of a transistor
- Patent number 6,403,979
- Issue date Jun 11, 2002
- Advanced Micro Devices, Inc.
- Daniel Kadosh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of silicide formation by silicon pretreatment
- Patent number 6,399,493
- Issue date Jun 4, 2002
- Advanced Micro Devices, Inc.
- Robert Dawson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Parallel and series-coupled transistors having gate conductors form...
- Patent number 6,383,872
- Issue date May 7, 2002
- Advanced Micro Devices, Inc.
- Daniel Kadosh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Angled halo implant tailoring using implant mask
- Patent number 6,372,587
- Issue date Apr 16, 2002
- Advanced Micro Devices, Inc.
- Jon D. Cheek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure for determining the properties of densely packed tra...
- Patent number 6,359,461
- Issue date Mar 19, 2002
- Advanced Micro Devices, Inc.
- John J. Bush
- G01 - MEASURING TESTING
Information Patent Grant
Method of fabricating a deep source/drain
- Patent number 6,358,803
- Issue date Mar 19, 2002
- Advanced Micro Devices, Inc.
- Mark Michael
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for characterizing semiconductor device perfor...
- Patent number 6,346,426
- Issue date Feb 12, 2002
- Advanced Micro Devices, Inc.
- Anthony J. Toprac
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Embedded NVM in a HKMG Process
- Publication number 20150194439
- Publication date Jul 9, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Jon D. Cheek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Embedded NVM in a HKMG Process
- Publication number 20140225176
- Publication date Aug 14, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Jon D. Cheek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT
- Publication number 20100190354
- Publication date Jul 29, 2010
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT
- Publication number 20070218618
- Publication date Sep 20, 2007
- FREESCALE SEMICONDUCTOR, INC.
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low-power multiple-channel fully depleted quantum well CMOSFETs
- Publication number 20060278938
- Publication date Dec 14, 2006
- Advanced Micro Devices, Inc.
- James N. Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interlayer dielectric under stress for an integrated circuit
- Publication number 20060226490
- Publication date Oct 12, 2006
- James D. Burnett
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device and method of making semiconductor device comp...
- Publication number 20060118918
- Publication date Jun 8, 2006
- Advanced Micro Devices, Inc.
- Andrew Michael Waite
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicon-on-insulator semiconductor device with silicon layers havin...
- Publication number 20060091427
- Publication date May 4, 2006
- Advanced Micro Devices, Inc.
- Andrew M. Waite
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of reducing STI divot formation during semiconductor device...
- Publication number 20050196928
- Publication date Sep 8, 2005
- Advanced Micro Devices, Inc.
- Douglas J. Bonser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low-power multiple-channel fully depleted quantum well CMOSFETs
- Publication number 20050104140
- Publication date May 19, 2005
- Advanced Micro Devices, Inc.
- James N. Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming resistive structures
- Publication number 20040235258
- Publication date Nov 25, 2004
- David Donggang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor component and method of manufacture
- Publication number 20040087094
- Publication date May 6, 2004
- Advanced Micro Devices, Inc.
- Derick Wristers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming silicide contacts and device incorporation same
- Publication number 20020137268
- Publication date Sep 26, 2002
- John G. Pellerin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA SHORT CHANNEL LENGTH DICTATED BY THE WIDTH OF A SACRIFICIAL S...
- Publication number 20020003272
- Publication date Jan 10, 2002
- MARK I. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY MEMORY CELL ASSEMBLY AND METHODS
- Publication number 20010020716
- Publication date Sep 13, 2001
- MARK I. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS

Jon C. Cheek

Person

Patents Grantslast 30 patents

Embedded NVM in a HKMG process

Embedded NVM in a HKMG process

Semiconductor device and method of making semiconductor device comp...

Methodology to reduce SOI floating-body effect

Low-power multiple-channel fully depleted quantum well CMOSFETs

Interlayer dielectric under stress for an integrated circuit

Silicon-on-insulator semiconductor device with silicon layers havin...

Method of manufacturing a semiconductor component

Method for offsetting a silicide process from a gate electrode of a...

Method of reducing STI divot formation during semiconductor device...

Low-power multiple-channel fully depleted quantum well CMOSFETs

Method for manufacturing a semiconductor component having an early...

Method of forming silicide layers over a plurality of semiconductor...

Method of forming source/drain regions in a semiconductor device

Semiconductor structure having elevated salicided source/drain regi...

Semiconductor structure having a metal gate electrode and elevated...

Transistor device having an enhanced width dimension and a method o...

Self-aligned VT implant

Method of making transistors with gate insulation layers of differi...

Removable spacer technique

Method of analyzing the effects of shadowing of angled halo implants

High density memory cell assembly and methods

Method of controlling junction recesses in a semiconductor device

Test structure for measuring effective channel length of a transistor

Method of silicide formation by silicon pretreatment

Parallel and series-coupled transistors having gate conductors form...

Angled halo implant tailoring using implant mask

Test structure for determining the properties of densely packed tra...

Method of fabricating a deep source/drain

Method and apparatus for characterizing semiconductor device perfor...

Patents Applicationslast 30 patents

Embedded NVM in a HKMG Process

Embedded NVM in a HKMG Process

INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT

INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT

Low-power multiple-channel fully depleted quantum well CMOSFETs

Interlayer dielectric under stress for an integrated circuit

Semiconductor device and method of making semiconductor device comp...

Silicon-on-insulator semiconductor device with silicon layers havin...

Method of reducing STI divot formation during semiconductor device...

Low-power multiple-channel fully depleted quantum well CMOSFETs

Method of forming resistive structures

Semiconductor component and method of manufacture

Method of forming silicide contacts and device incorporation same

ULTRA SHORT CHANNEL LENGTH DICTATED BY THE WIDTH OF A SACRIFICIAL S...

HIGH DENSITY MEMORY CELL ASSEMBLY AND METHODS