Josef Schnell

Person

Charlotte, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-chip package with interconnected stacked chips
- Patent number 8,138,610
- Issue date Mar 20, 2012
- Qimonda AG
- Jong Hoon Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory refresh system and method
- Patent number 7,975,170
- Issue date Jul 5, 2011
- Qimonda AG
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and structure of expanding, upgrading, or fixing multi-chip...
- Patent number 7,944,047
- Issue date May 17, 2011
- Qimonda AG
- Jong Hoon Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for synchronizing memory enabled systems with...
- Patent number 7,882,324
- Issue date Feb 1, 2011
- Qimonda AG
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for implementing memory enabled systems using...
- Patent number 7,721,010
- Issue date May 18, 2010
- Qimonda North America Corp.
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-diagnostic scheme for detecting errors
- Patent number 7,694,196
- Issue date Apr 6, 2010
- Qimonda North America Corp.
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure to share internally generated voltages between chips in MCP
- Patent number 7,688,665
- Issue date Mar 30, 2010
- Qimonda North America Corp.
- Jung Pill Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory configured on a common substrate
- Patent number 7,539,034
- Issue date May 26, 2009
- Qimonda North America Corp.
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Edge pad architecture for semiconductor memory
- Patent number 7,405,957
- Issue date Jul 29, 2008
- Infineon Technologies AG
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Write burst stop function in low power DDR sDRAM
- Patent number 7,397,727
- Issue date Jul 8, 2008
- Infineon Technologies AG
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Boosted clock circuit for semiconductor memory
- Patent number 7,376,042
- Issue date May 20, 2008
- Qimonda AG
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Data strobe synchronization for DRAM devices
- Patent number 7,209,396
- Issue date Apr 24, 2007
- Infineon Technologies AG
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit chip having a first delay circuit trimmed via a...
- Patent number 7,187,599
- Issue date Mar 6, 2007
- Infineon Technologies North America Corp.
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay lock loop and update method with limited drift and improved p...
- Patent number 6,456,130
- Issue date Sep 24, 2002
- Infineon Technologies AG
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
DLL lock scheme with multiple phase detection
- Patent number 6,388,482
- Issue date May 14, 2002
- Infineon Technologies North America Corp.
- Josef Schnell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for performing a defect leakage screen test fo...
- Patent number 6,330,697
- Issue date Dec 11, 2001
- International Business Machines Corporation
- Michael P. Clinton
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE
- Publication number 20090200652
- Publication date Aug 13, 2009
- Jong Hoon Oh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS
- Publication number 20090129186
- Publication date May 21, 2009
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH...
- Publication number 20090113158
- Publication date Apr 30, 2009
- JOSEF SCHNELL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING MEMORY ENABLED SYSTEMS USING...
- Publication number 20090113078
- Publication date Apr 30, 2009
- JOSEF SCHNELL
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP...
- Publication number 20090079055
- Publication date Mar 26, 2009
- JONG HOON OH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP
- Publication number 20090080279
- Publication date Mar 26, 2009
- Jung Pill Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY REFRESH SYSTEM AND METHOD
- Publication number 20080313494
- Publication date Dec 18, 2008
- QIMONDA NORTH AMERICA CORP.
- Klaus Hummler
- G11 - INFORMATION STORAGE
Information Patent Application
Memory configured on a common substrate
- Publication number 20080189480
- Publication date Aug 7, 2008
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Memory including error correction code circuit
- Publication number 20080168331
- Publication date Jul 10, 2008
- Thomas Vogelsang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory with data clock receiver and command/address clock receiver
- Publication number 20080137470
- Publication date Jun 12, 2008
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
Memory including first and second receivers
- Publication number 20080137472
- Publication date Jun 12, 2008
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with clock distribution options
- Publication number 20080137471
- Publication date Jun 12, 2008
- Josef Schnell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CONFIGURING A MEMORY DEVICE
- Publication number 20080098152
- Publication date Apr 24, 2008
- Josef Schnell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Boosted clock circuit for semiconductor memory
- Publication number 20080031057
- Publication date Feb 7, 2008
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
Clock circuit for semiconductor memory
- Publication number 20070291572
- Publication date Dec 20, 2007
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for temperature compensating off chip driver (...
- Publication number 20070252638
- Publication date Nov 1, 2007
- Farrukh Aquil
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Edge pad architecture for semiconductor memory
- Publication number 20070165439
- Publication date Jul 19, 2007
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
Memory having status register read function
- Publication number 20070162713
- Publication date Jul 12, 2007
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
Write burst stop function in low power DDR sDRAM
- Publication number 20070147142
- Publication date Jun 28, 2007
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit chip having a first delay circuit trimmed via a...
- Publication number 20060268632
- Publication date Nov 30, 2006
- Josef Schnell
- G01 - MEASURING TESTING
Information Patent Application
Data strobe synchronization for DRAM devices
- Publication number 20060193194
- Publication date Aug 31, 2006
- Josef Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
DELAY LOCK LOOP AND UPDATE METHOD WITH LIMITED DRIFT AND IMPROVED P...
- Publication number 20020125926
- Publication date Sep 12, 2002
- Josef Schnell
- G11 - INFORMATION STORAGE

Josef Schnell

Person

Patents Grantslast 30 patents

Multi-chip package with interconnected stacked chips

Memory refresh system and method

Method and structure of expanding, upgrading, or fixing multi-chip...

Method and apparatus for synchronizing memory enabled systems with...

Method and apparatus for implementing memory enabled systems using...

Self-diagnostic scheme for detecting errors

Structure to share internally generated voltages between chips in MCP

Memory configured on a common substrate

Edge pad architecture for semiconductor memory

Write burst stop function in low power DDR sDRAM

Boosted clock circuit for semiconductor memory

Data strobe synchronization for DRAM devices

Integrated circuit chip having a first delay circuit trimmed via a...

Delay lock loop and update method with limited drift and improved p...

DLL lock scheme with multiple phase detection

Apparatus and method for performing a defect leakage screen test fo...

Patents Applicationslast 30 patents

METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE

SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS

METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH...

METHOD AND APPARATUS FOR IMPLEMENTING MEMORY ENABLED SYSTEMS USING...

METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP...

STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP

MEMORY REFRESH SYSTEM AND METHOD

Memory configured on a common substrate

Memory including error correction code circuit

Memory with data clock receiver and command/address clock receiver

Memory including first and second receivers

Memory with clock distribution options

METHOD AND APPARATUS FOR CONFIGURING A MEMORY DEVICE

Boosted clock circuit for semiconductor memory

Clock circuit for semiconductor memory

Method and apparatus for temperature compensating off chip driver (...

Edge pad architecture for semiconductor memory

Memory having status register read function

Write burst stop function in low power DDR sDRAM

Integrated circuit chip having a first delay circuit trimmed via a...

Data strobe synchronization for DRAM devices

DELAY LOCK LOOP AND UPDATE METHOD WITH LIMITED DRIFT AND IMPROVED P...