Patent Application
20070291572
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
In one embodiment memory device 10 is a low power DRAM chip, such as a low power DDR SDRAM. Bank 0, bank 1, bank 2, and bank 3 are organized in a square or rectangular-shaped configuration on the semiconductor memory device 10. In some cases, data pads and command and address pads are then physically located adjacent the edge of the semiconductor chip (as illustrated in
In one embodiment, first region 12 includes data pads (“DQ pads”) and off-chip drivers (“OCD”) 31, and second region 14 includes command and address pads 32a/32b, clock pads 30a and 30b. The DQ pads and OCD 31, the command and address pads 32a/32b, and the clock pads 30a and 30b are each coupled to buffer and multiplexing logic and the data path.
In operation, command and address pads 32a/32b receive command and address signals for retrieving data from the various memory banks (bank0, bank 1, bank 2, and bank 3) in memory device 10. Data is then retrieved from the various memory banks via DQ pads 31 in first region 12. DQ pads 31 are coupled to paths that allow data to be transmitted off memory device 10. Clock pads 30a and 30b in second region 14 are configured to receive differential clock signals VCLK and VbCLK from off memory device 10, such as from a memory controller or other device coupled to memory device 10. These clock signals are then used to drive clock tree 16, which in turn drives the DQ pads and OCD 31 in first region 12.
In one embodiment, clock tree 16 is coupled between first region 12 and second region 14 and it includes buffer 20 and first and second inverters 22 and 24. Metal wires connected between buffer 20 and first and inverter 22 and between first and second inverters 22 and 24 are illustrated with arrows. In some cases, the distance between first region 12 and second region 14 is small, or first and second regions are located in the essentially the same area on memory device 10. In other cases, however, the distance between first region 12 and second region 14 is significant, and thus, requires that clock tree 16 has a significant distance. In such cases, the metal wires between buffer 20 and first and second inverters 22 and 24 also have significant length. As such, power loss can be significant as buffer 20 and inverters 22 and 24 drive the long metal wires of clock tree 16.
In one embodiment, second region 14 further includes clock control circuit 35. In one embodiment, clock control circuit 35 is configured to receive the differential clock signals VCLK and VbCLK and is further configured to regulate these signals. In one embodiment, clock control circuit 35 regulates the VCLK and VbCLK clock signals so that clock tree 16 is activated for the read data only during a read operation. Outside the read operation, clock tree is not driven. Such regulation of clock tree 16 reduces power consumed by memory device 10.
In one embodiment, clock control circuit 35 regulates the VCLK and VbCLK clock signals in accordance with control signals from read control circuit 36, which is also provided on memory device 10. Among other signals, read control circuit 36 generates a READ signal, a DQSENshift signal and a SET signal. These signals from read control circuit 36 are provided to clock control circuit 35, which then uses these signals to control VCLK and VbCLK clock signals in order to decrease power consumption by activating clock tree 16 for the read data only during a read operation.
In one embodiment, memory device 10 is a semiconductor memory chip package, such that DQ pads 31 in first region 12 are located along a first edge of the chip package and such that command and address pads 32a/32b in second region 14 are located along a second edge of the chip package opposite the first edge. In another embodiment, memory device 10 is a semiconductor wafer or die. In that case, DQ pads 31 in first region 12 are located along a first of the semiconductor wafer or die and command and address pads 32a/32b in second region 14 are located along a second edge of the semiconductor wafer or die. In either case, where first and second regions 12 and 14 are separated across the chip or wafer, metal lines with clock tree 16 will have significant length, and thus, significant power loss when driven.
Data clock receiver 40 is configured to receive differential clock signals VCLK and VbCLK as well as a BANKACTIVE signal. As indicated earlier, the VCLK and VbCLK clock signals are differential clock signal received from off the memory chip 10, such as from a memory controller or the like. The BANKACTIVE signal is a signal that transitions each time a memory bank is selected to be accessed. Responsive to these received signals, data clock receiver 40 is further configured to generate an ICLK signal and provide it to both buffer enable logic 42 and to clock buffer 44.
Buffer enable logic 42 is configured to receive the ICLK signal generated by data clock receiver 40, and is further configured to receive a READ signal, a DQSENshift signal, and a SET signal. The READ signal is the read command signal that is internal to memory device 10 that transitions high when a read command is asserted. The DQSENshift signal is the DQ enable signal shifted in time in order to account for latencies and yet still capture data during a read. The SET signal resets buffer enable logic 42 when needed, such as during a power up. The ICLK signal drives buffer enable logic 42 to produce an ENDP enable signal that is then received by clock buffer 44.
Clock buffer 44 receives the ICLK signal from data clock receiver 40 and the ENDP signal from buffer enable logic 42 and in turn generates a CLKREAD signal. The CLKREAD signal serves as the read clock signal that drives the clock tree 16. The ENDP signal enables and disables the clock buffer, generating the CLKREAD signal when enabled. The CLKREAD signal drives clock tree 16 for the read data only during a read operation so that less power is consumed by clock tree 16 than would be when differential clock signals VCLK and VbCLK are coupled directly to, and drive, clock tree 16.
In order to further illustrate the embodiment of
In
The internal READ command signal and the DQSEN signal are active high while a read operation is ongoing. The DQSENshift signal is generated from the DQSEN signal and shifted by a number of clock cycles. This shifted signal allows for latencies during the read cycle. When the internal READ command signal goes high, this causes the ENDP signal to go high (illustrated by arrow 50 in
The low-going transition of DQSEN signal indicates the when the read burst is completed. The clock buffer 44 is not disabled with the low-going transition of DQSEN signal, however. Instead, it is the low-going transition of the DQSENshift signal that disables clock buffer 44, as illustrated with arrow 52 in
As such, the CLKREAD signal is only active while the ENDP signal is active high during a read burst operation. This active period is defined between the high-going transition of the DQSEN signal until the low-going transition of the DQSENshift signal (illustrated between the arrows 54a and 54b in
As is evident from timing signals in
For example, in situations where the differential clock signals VCLK and VbCLK directly drive clock tree 16, once the BANKACTIVE signal goes active when memory chip 10 is active, clock tree 16 is constantly driven and consumes significant power. By inserting clock control circuit 35 on memory device 10, the driving of clock tree 16 can be interrupted outside of a read operation even when memory chip 10 is active. Interrupting clock tree 16 saves significant power, which can be especially significant in low power applications.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
