Joseph C. Sher

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Clamp circuit with fuse options
- Patent number 7,468,623
- Issue date Dec 23, 2008
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for measuring and forcing an internal voltage of...
- Patent number 6,946,863
- Issue date Sep 20, 2005
- Micron Technology, Inc.
- Daniel R. Loughmiller
- G11 - INFORMATION STORAGE
Information Patent Grant
System for testing integrated circuit devices
- Patent number 6,930,503
- Issue date Aug 16, 2005
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
Clamp circuit with fuse options
- Patent number 6,885,238
- Issue date Apr 26, 2005
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
System for testing integrated circuit devices
- Patent number 6,756,805
- Issue date Jun 29, 2004
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
Device and method for limiting the extent to which circuits in inte...
- Patent number 6,633,196
- Issue date Oct 14, 2003
- Micron Technology, Inc.
- Joseph C. Sher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for ESD protection in semiconductor chips
- Patent number 6,586,290
- Issue date Jul 1, 2003
- Micron Technology, Inc.
- Stephen L. Casper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Local substrate pumping in integrated circuits
- Patent number 6,507,235
- Issue date Jan 14, 2003
- Micron Technology, Inc.
- Joseph C. Sher
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Structure for ESD protection in semiconductor chips
- Patent number 6,507,074
- Issue date Jan 14, 2003
- Micron Technology, Inc.
- Stephen L. Casper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for adjusting an output slew rate of a buffer
- Patent number 6,504,396
- Issue date Jan 7, 2003
- Micron Technology, Inc.
- Joseph C. Sher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System for testing integrated circuit devices
- Patent number 6,496,027
- Issue date Dec 17, 2002
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits and methods for testing memory cells along a periphery of...
- Patent number 6,459,634
- Issue date Oct 1, 2002
- Micron Technology, Inc.
- Joseph Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage independent fuse circuit and method
- Patent number 6,449,207
- Issue date Sep 10, 2002
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for generating a clock within a semiconductor...
- Patent number 6,445,644
- Issue date Sep 3, 2002
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
Device and method for limiting the extent to which circuits in inte...
- Patent number 6,417,721
- Issue date Jul 9, 2002
- Micron Technology, Inc.
- Joseph C. Sher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clamp circuit with fuse options
- Patent number 6,351,180
- Issue date Feb 26, 2002
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having isolated anti-fuse structures and method...
- Patent number 6,307,249
- Issue date Oct 23, 2001
- Micron Technology, Inc.
- Joseph C. Sher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer with adjustable slew rate and a method of providing an adjus...
- Patent number 6,300,788
- Issue date Oct 9, 2001
- Micron Technology, Inc.
- Joseph C. Sher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device and method for limiting the extent to which circuits in inte...
- Patent number 6,285,237
- Issue date Sep 4, 2001
- Micron Technology, Inc.
- Joseph C. Sher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Voltage independent fuse circuit and method
- Patent number 6,266,291
- Issue date Jul 24, 2001
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
Local substrate pumping in integrated circuits
- Patent number 6,242,969
- Issue date Jun 5, 2001
- Micron Technology, Inc.
- Joseph C. Sher
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Method for fabricating isolated anti-fuse structure
- Patent number 6,242,335
- Issue date Jun 5, 2001
- Micron Technology, Inc.
- Joseph C. Sher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit and method for measuring and forcing an internal voltage of...
- Patent number 6,229,296
- Issue date May 8, 2001
- Micron Technology, Inc.
- Kevin G. Duesman
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method for generating a clock within a semiconductor...
- Patent number 6,169,704
- Issue date Jan 2, 2001
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer with adjustable slew rate and a method of providing an adjus...
- Patent number 6,157,204
- Issue date Dec 5, 2000
- Micron Technology, Inc.
- Joseph C. Sher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory repair
- Patent number 6,154,851
- Issue date Nov 28, 2000
- Micron Technology, Inc.
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Grant
Isolated anti-fuse structure and method for fabricating same
- Patent number 6,140,692
- Issue date Oct 31, 2000
- Micron Technology, Inc.
- Joseph C. Sher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Well resistor for ESD protection of CMOS circuits
- Patent number 6,137,664
- Issue date Oct 24, 2000
- Micron Technology, Inc.
- Stephen L. Casper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit and method for measuring and forcing an internal voltage of...
- Patent number 6,117,696
- Issue date Sep 12, 2000
- Micron Technology, Inc.
- Daniel R. Loughmiller
- G01 - MEASURING TESTING
Information Patent Grant
Voltage compensating CMOS input buffer circuit
- Patent number 6,069,492
- Issue date May 30, 2000
- Micron Technology, Inc.
- Joseph C. Sher
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
System for testing integrated circuit devices
- Publication number 20050270058
- Publication date Dec 8, 2005
- Micron Technology, Inc.
- Joseph C. Sher
- G01 - MEASURING TESTING
Information Patent Application
System for testing integrated circuit devices
- Publication number 20040201399
- Publication date Oct 14, 2004
- Micron Technology, Inc.
- Joseph C. Sher
- G01 - MEASURING TESTING
Information Patent Application
Clamp circuit with fuse options
- Publication number 20040027190
- Publication date Feb 12, 2004
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Application
System for testing integrated circuit devices
- Publication number 20030090285
- Publication date May 15, 2003
- Micron Technology, Inc.
- Joseph C. Sher
- G01 - MEASURING TESTING
Information Patent Application
Device and method for limiting the extent to which circuits in inte...
- Publication number 20020175741
- Publication date Nov 28, 2002
- Joseph C. Sher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure for ESD proctection in semiconductor chips
- Publication number 20020047165
- Publication date Apr 25, 2002
- Micron Technology, Inc.
- Stephen L. Casper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Clamp circuit with fuse options
- Publication number 20020030539
- Publication date Mar 14, 2002
- Micron Technology, Inc.,
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Application
Buffer with adjustable slew rate and a method of providing an adjus...
- Publication number 20020030511
- Publication date Mar 14, 2002
- Joseph C. Sher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage independent fuse circuit and method
- Publication number 20010046170
- Publication date Nov 29, 2001
- Joseph C. Sher
- G11 - INFORMATION STORAGE
Information Patent Application
Device and method for limiting the extent to which circuits in inte...
- Publication number 20010026185
- Publication date Oct 4, 2001
- Joseph C. Sher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus and method for generating a clock within a semiconductor...
- Publication number 20010011913
- Publication date Aug 9, 2001
- Joseph C. Sher
- G11 - INFORMATION STORAGE

Joseph C. Sher

Person

Patents Grantslast 30 patents

Clamp circuit with fuse options

Circuit and method for measuring and forcing an internal voltage of...

System for testing integrated circuit devices

Clamp circuit with fuse options

System for testing integrated circuit devices

Device and method for limiting the extent to which circuits in inte...

Structure for ESD protection in semiconductor chips

Local substrate pumping in integrated circuits

Structure for ESD protection in semiconductor chips

Method for adjusting an output slew rate of a buffer

System for testing integrated circuit devices

Circuits and methods for testing memory cells along a periphery of...

Voltage independent fuse circuit and method

Apparatus and method for generating a clock within a semiconductor...

Device and method for limiting the extent to which circuits in inte...

Clamp circuit with fuse options

Integrated circuit having isolated anti-fuse structures and method...

Buffer with adjustable slew rate and a method of providing an adjus...

Device and method for limiting the extent to which circuits in inte...

Voltage independent fuse circuit and method

Local substrate pumping in integrated circuits

Method for fabricating isolated anti-fuse structure

Circuit and method for measuring and forcing an internal voltage of...

Apparatus and method for generating a clock within a semiconductor...

Buffer with adjustable slew rate and a method of providing an adjus...

Memory repair

Isolated anti-fuse structure and method for fabricating same

Well resistor for ESD protection of CMOS circuits

Circuit and method for measuring and forcing an internal voltage of...

Voltage compensating CMOS input buffer circuit

Patents Applicationslast 30 patents

System for testing integrated circuit devices

System for testing integrated circuit devices

Clamp circuit with fuse options

System for testing integrated circuit devices

Device and method for limiting the extent to which circuits in inte...

Structure for ESD proctection in semiconductor chips

Clamp circuit with fuse options

Buffer with adjustable slew rate and a method of providing an adjus...

Voltage independent fuse circuit and method

Device and method for limiting the extent to which circuits in inte...

Apparatus and method for generating a clock within a semiconductor...