Juergen Lahner

Person

Morgan Hill, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Statistical design closure
- Patent number 7,895,546
- Issue date Feb 22, 2011
- LSI Corporation
- Juergen K. Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing test code generation for verification environment
- Patent number 7,844,929
- Issue date Nov 30, 2010
- LSI Corporation
- Kavitha Chaturvedula
- G01 - MEASURING TESTING
Information Patent Grant
Enhanced method of optimizing multiplex structures and multiplex co...
- Patent number 7,594,201
- Issue date Sep 22, 2009
- LSI Corporation
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-the-fly RTL instructor for advanced DFT and design closure
- Patent number 7,441,210
- Issue date Oct 21, 2008
- LSI Corporation
- Juergen K. Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and computer program for incremental placement and routing w...
- Patent number 7,415,687
- Issue date Aug 19, 2008
- LSI Corporation
- Juergen K. Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and computer program for management of synchronous and async...
- Patent number 7,412,678
- Issue date Aug 12, 2008
- LSI Corporation
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of associating timing violations with critical structures in...
- Patent number 7,380,228
- Issue date May 27, 2008
- LSI Corporation
- Randall P. Fry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of optimizing RTL code for multiplex structures
- Patent number 7,086,015
- Issue date Aug 1, 2006
- LSI Logic Corporation
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated analysis of RTL code containing ASIC vendor rules
- Patent number 7,082,584
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized buffering for JTAG boundary scan nets
- Patent number 7,000,163
- Issue date Feb 14, 2006
- LSI Logic Corporation
- Juergen Dirks
- G01 - MEASURING TESTING
Information Patent Grant
Advanced design format library for integrated circuit design synthe...
- Patent number 6,990,651
- Issue date Jan 24, 2006
- LSI Logic Corporation
- Balamurugan Balasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Congestion estimation for register transfer level code
- Patent number 6,907,588
- Issue date Jun 14, 2005
- LSI Logic Corporation
- Balamurugan Balasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer cell insertion and electronic design automation
- Patent number 6,766,499
- Issue date Jul 20, 2004
- LSI Logic Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Length matrix generator for register transfer level code
- Patent number 6,757,885
- Issue date Jun 29, 2004
- LSI Logic Corporation
- Srinivas Adusumalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit having on-chip capacitors for supplying power to...
- Patent number 6,546,538
- Issue date Apr 8, 2003
- LSI Logic Corporation
- Shalini Rubdi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell interconnect delay library for integrated circuit design
- Patent number 6,532,576
- Issue date Mar 11, 2003
- LSI Logic Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RTL code optimization for resource sharing structures
- Patent number 6,438,730
- Issue date Aug 20, 2002
- LSI Logic Corporation
- Kiran Atmakuri
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ADVANCED PHYSICAL SIMULATOR
- Publication number 20100217564
- Publication date Aug 26, 2010
- Juergen K. Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimizing test code generation for verification environment
- Publication number 20090282307
- Publication date Nov 12, 2009
- Kavitha Chaturvedula
- G01 - MEASURING TESTING
Information Patent Application
Statistical design closure
- Publication number 20090063564
- Publication date Mar 5, 2009
- Juergen K. Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-the-fly RTL instructor for advanced DFT and design closure
- Publication number 20070083839
- Publication date Apr 12, 2007
- LSI Logic Corporation
- Juergen K. Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and computer program for analysis of an integrated circuit d...
- Publication number 20070079266
- Publication date Apr 5, 2007
- LSI Logic Corporation
- Krishna Devineni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and computer program for incremental placement and routing w...
- Publication number 20070079273
- Publication date Apr 5, 2007
- LSI Logic Corporation
- Juergen K. Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCED METHOD OF OPTIMIZING MULTIPLEX STRUCTURES AND MULTIPLEX CO...
- Publication number 20060282801
- Publication date Dec 14, 2006
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of associating timing violations with critical structures in...
- Publication number 20060101363
- Publication date May 11, 2006
- LSI Logic Corporation
- Randall P. Fry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and computer program for management of synchronous and async...
- Publication number 20050273741
- Publication date Dec 8, 2005
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of optimizing RTL code for multiplex structures
- Publication number 20050257180
- Publication date Nov 17, 2005
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Advanced design format library for integrated circuit design synthe...
- Publication number 20040230919
- Publication date Nov 18, 2004
- Balamurugan Balasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automated analysis of RTL code containing ASIC vendor rules
- Publication number 20040221249
- Publication date Nov 4, 2004
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Congestion estimation for register transfer level code
- Publication number 20040128639
- Publication date Jul 1, 2004
- LSI Logic Corporation
- Balamurugan Balasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LENGTH MATRIX GENERATOR FOR REGISTER TRANSFER LEVEL CODE
- Publication number 20040128640
- Publication date Jul 1, 2004
- Srinivas Adusumalli
- G06 - COMPUTING CALCULATING COUNTING

Juergen Lahner

Person

Patents Grantslast 30 patents

Statistical design closure

Optimizing test code generation for verification environment

Enhanced method of optimizing multiplex structures and multiplex co...

On-the-fly RTL instructor for advanced DFT and design closure

Method and computer program for incremental placement and routing w...

Method and computer program for management of synchronous and async...

Method of associating timing violations with critical structures in...

Method of optimizing RTL code for multiplex structures

Automated analysis of RTL code containing ASIC vendor rules

Optimized buffering for JTAG boundary scan nets

Advanced design format library for integrated circuit design synthe...

Congestion estimation for register transfer level code

Buffer cell insertion and electronic design automation

Length matrix generator for register transfer level code

Integrated circuit having on-chip capacitors for supplying power to...

Cell interconnect delay library for integrated circuit design

RTL code optimization for resource sharing structures

Patents Applicationslast 30 patents

ADVANCED PHYSICAL SIMULATOR

Optimizing test code generation for verification environment

Statistical design closure

On-the-fly RTL instructor for advanced DFT and design closure

Method and computer program for analysis of an integrated circuit d...

Method and computer program for incremental placement and routing w...

ENHANCED METHOD OF OPTIMIZING MULTIPLEX STRUCTURES AND MULTIPLEX CO...

Method of associating timing violations with critical structures in...

Method and computer program for management of synchronous and async...

Method of optimizing RTL code for multiplex structures

Advanced design format library for integrated circuit design synthe...

Automated analysis of RTL code containing ASIC vendor rules

Congestion estimation for register transfer level code

LENGTH MATRIX GENERATOR FOR REGISTER TRANSFER LEVEL CODE