Kalipatnam V. Rao

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of simultaneous fabrication of isolation and gate regions in...
- Patent number 6,239,003
- Issue date May 29, 2001
- Texas Instruments Incorporated
- Kalipatnam V. Rao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sidewall-sealed poly-buffered LOCOS isolation
- Patent number 5,369,051
- Issue date Nov 29, 1994
- Texas Instruments Incorporated
- Kalipatnam V. Rao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sidewall-sealed poly-buffered LOCOS isolation
- Patent number 5,159,428
- Issue date Oct 27, 1992
- Texas Instruments Incorporated
- Kalipatnam V. Rao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interlevel dielectric process
- Patent number 5,114,530
- Issue date May 19, 1992
- Texas Instruments Incorporated
- Kalipatnam V. Rao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reduction of filaments between electrodes
- Patent number 4,878,996
- Issue date Nov 7, 1989
- Texas Instruments Incorporated
- Allan T. Mitchell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating integrated circuit structure with extremely...
- Patent number 4,874,716
- Issue date Oct 17, 1989
- Texas Instrument Incorporated
- Kalipatnam V. Rao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of sidewall oxide to reduce filaments
- Patent number 4,806,201
- Issue date Feb 21, 1989
- Texas Instruments Incorporated
- Allan T. Mitchell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interlevel dielectric fabrication process
- Patent number 4,799,992
- Issue date Jan 24, 1989
- Texas Instruments Incorporated
- Kalipatnam V. Rao
- H01 - BASIC ELECTRIC ELEMENTS

Kalipatnam V. Rao

Person

Patents Grantslast 30 patents

Method of simultaneous fabrication of isolation and gate regions in...

Sidewall-sealed poly-buffered LOCOS isolation

Sidewall-sealed poly-buffered LOCOS isolation

Interlevel dielectric process

Method for reduction of filaments between electrodes

Process for fabricating integrated circuit structure with extremely...

Use of sidewall oxide to reduce filaments

Interlevel dielectric fabrication process