Kamal Dalmia

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Linearized digital phase-locked loop
- Patent number 6,993,105
- Issue date Jan 31, 2006
- Cypress Semiconductor Corp.
- Terry D. Little
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Linearized digital phase-locked loop method
- Patent number 6,950,484
- Issue date Sep 27, 2005
- Cypress Semiconductor Corp.
- Timothy D. Jordan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Linearized digital phase-locked loop
- Patent number 6,711,226
- Issue date Mar 23, 2004
- Cypress Semiconductor Corp.
- Bertrand J. Williams
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital phase/frequency detector, and clock generator and data reco...
- Patent number 6,683,930
- Issue date Jan 27, 2004
- Cypress Semiconductor Corp.
- Kamal Dalmia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Linearized digital phase-locked loop method
- Patent number 6,535,023
- Issue date Mar 18, 2003
- Cypress Semiconductor Corp.
- Bertrand J. Williams
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Linearized digital phase-locked loop method
- Patent number 6,417,698
- Issue date Jul 9, 2002
- Cypress Semiconductor Corp.
- Bertrand J. Williams
- G11 - INFORMATION STORAGE
Information Patent Grant
Linearized digital phase-locked loop
- Patent number 6,366,145
- Issue date Apr 2, 2002
- Cypress Semiconductor Corp.
- Bertrand J. Williams
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Data frequency detector
- Patent number 6,366,135
- Issue date Apr 2, 2002
- Cypress Semiconductor Corp.
- Kamal Dalmia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reference-free clock generation and data recovery PLL
- Patent number 6,310,521
- Issue date Oct 30, 2001
- Cypress Semiconductor Corp.
- Kamal Dalmia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reference-free clock generator and data recovery PLL
- Patent number 6,307,413
- Issue date Oct 23, 2001
- Cypress Semiconductor Corp.
- Kamal Dalmia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed, multiple-input multiplexer scheme
- Patent number 6,239,646
- Issue date May 29, 2001
- Cypress Semiconductor Corp.
- Mohammad J. Navabi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase detector
- Patent number 6,225,831
- Issue date May 1, 2001
- Cypress Semiconductor Corp.
- Kamal Dalmia
- G01 - MEASURING TESTING
Information Patent Grant
Clock and data recovery PLL based on parallel architecture
- Patent number 6,211,741
- Issue date Apr 3, 2001
- Cypress Semiconductor Corp.
- Kamal Dalmia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase detector with extended linear range
- Patent number 6,100,722
- Issue date Aug 8, 2000
- Cypress Semiconductor Corp.
- Kamal Dalmia
- G01 - MEASURING TESTING
Information Patent Grant
Phase detector with extended linear range
- Patent number 6,075,388
- Issue date Jun 13, 2000
- Cypress Semiconductor Corp.
- Kamal Dalmia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method, architecture and circuit for half-rate clock and/or data re...
- Patent number 6,075,416
- Issue date Jun 13, 2000
- Cypress Semiconductor Corp.
- Kamal Dalmia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase detector
- Patent number 6,072,337
- Issue date Jun 6, 2000
- Cypress Semiconductor Corp.
- Kamal Dalmia
- G01 - MEASURING TESTING

Kamal Dalmia

Person

Patents Grantslast 30 patents

Linearized digital phase-locked loop

Linearized digital phase-locked loop method

Linearized digital phase-locked loop

Digital phase/frequency detector, and clock generator and data reco...

Linearized digital phase-locked loop method

Linearized digital phase-locked loop method

Linearized digital phase-locked loop

Data frequency detector

Reference-free clock generation and data recovery PLL

Reference-free clock generator and data recovery PLL

High-speed, multiple-input multiplexer scheme

Phase detector

Clock and data recovery PLL based on parallel architecture

Phase detector with extended linear range

Phase detector with extended linear range

Method, architecture and circuit for half-rate clock and/or data re...

Phase detector